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user?s manual, v 0.1, jan 2005 microcontrollers never stop thinking. XC800 microcontroller family architecture and instruction set
edition 2005-01 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in lif e-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
user?s manual, v 0.1, jan 2005 microcontrollers never stop thinking. XC800 microcontroller family architecture and instruction set
XC800 revision history: 2005-01 v 0.1 previous version: - page subjects (major change s since last revision) we listen to your comments any information within this do cument that you feel is wron g, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to th is document) to: mcdocu.comments@infineon.com
XC800 user?s manual, v 0.1 i-1 2005-01 1 fundamental structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 foreword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3.1 memory extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3.1.1 memory extension stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3.1.2 memory extension effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3.2 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.3 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.3.1 internal data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.3.2 internal data memory xram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.3.3 external data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.4 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3.4.1 special function register extension by mapping . . . . . . . . . . . . . . . . 7 1.3.4.2 special function register extension by paging . . . . . . . . . . . . . . . . . 8 1.4 bit protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 cpu architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 cpu register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.1 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.2 data pointer (dptr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.3 accumulator (acc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.4 b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1.5 program status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.6 extended operation register (eo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.7 memory extension registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.8 power control register (pcon) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.9 uart registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.10 timer/counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.11 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 on-chip debug support concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 basic interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.1 interrupt source and vector address . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.2 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 interrupt response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 service order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3cpu timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3.1 instruction timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3.2 accessing external memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2.1 accessing external program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.2.2 accessing external da ta memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 XC800 table of contents page
XC800 user?s manual, v 0.1 i-2 2005-01 4 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4.1 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4.2 introduction to the instruction se t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4.3 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.3.1 affected flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4.3.2 instruction table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3.3 instruction definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table of contents page
XC800 fundamental structure user?s manual, v 0.1 1-1 2005-01 1 fundamental structure 1.1 foreword this manual provides an overvi ew of the architecture and fu nctional characteristics of the XC800 microcontroller fami ly. it also includes a comple te description of the XC800 core instruction set. for detailed informati on on the different derivat ives of the XC800 8- bit microcontrollers, refer to the respective user?s manuals. 1.2 introduction the infineon XC800 micr ocontroller family has a cpu wh ich is functionally upward compatible to the 8051. while the standard 8051 core is designed around a 12-clock machine cycle, the XC800 core uses a two-clock period machine cycle. the instruction set consists of 45% one-byte, 41% two- byte, and 14% three-byte instructions. each instruction takes 1, 2 or 4 machine cycles to ex ecute. in case of access to slower memory, the access time may be ex tended by wait states. the XC800 microcontrollers su pport via the dedicated jtag interface or the standard uart interface, a range of debugging features including basic stop /start, single-step execution, breakpoint support and read/w rite access to the data memory, program memory and special function registers. the key features of the XC800 mi crocontrollers are listed below. features: ? two clocks per machine cycle ? program m emory d ownload option ? up to 1 mbyte of external data memory; up to 256 bytes of internal data memory ? up to 1 mbyte of program memory ? wait state support for slow memory ? support for synchronous or asynchronous pr ogram and data memory ? 15-source, 4-level interrupt controller ? up to eight data pointers ? power saving modes ? dedicated debug mode via the st andard jtag interface or uart ? two 16-bit timers (timer 0 and timer 1) ? full-duplex serial port (uart)
XC800 fundamental structure user?s manual, v 0.1 1-2 v 1.0, 2005-01 1.3 memory organization the memory partitioning of the XC800 mi crocontrollers is typical of the harvard architecture where data and program areas are held in se parate memory space. the on-chip peripheral units are accessed using an internal spec ial function register (sfr) memory area that occupies 128 bytes of address, whic h can be mapped or paged to increase the number of addressable sfrs. a typical memory map of the c ode space consists of intern al rom/flash, on-chip boot rom, an on-chip xram and/or external memory. the memory map of the data space is typical of the standard 8051 architecture: the internal dat a memory consists of 128 bytes of directly addressable internal ram (iram) , 128 bytes of indire ct addressable iram and an ?external? ram (xram) . external data memory may be supported outside of the internal range. figure 1-1 provides a general overview of the XC800 memory space and a typical memory map in user mode. figure 1-1 XC800 memory space and typi cal memory map in user mode extension stack ram memory extension stack pointer (mexsp) special function registers indirect address direct address 80 h ff h 00 h code space internal data space internal ram 7f h internal ram 0' 0000 h xram external data space 0' ffff h 0' f000 h 1' 0000 h 1' ffff h 2' 0000 h 2' ffff h 3' 0000 h 3' ffff h 4' 0000 h 4' ffff h 5' 0000 h 5' ffff h 6' 0000 h 6' ffff h 7' 0000 h 7' ffff h 8' 0000 h 8' ffff h 9' 0000 h 9' ffff h a' 0000 h a' ffff h b' 0000 h b' ffff h c' 0000 h c' ffff h d' 0000 h d' ffff h e' 0000 h e' ffff h f' 0000 h f' ffff h bank 1 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank a bank b bank c bank d bank e bank f bank 0 xram bank 2 0' c000 h bank 1 bank 3 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank a bank b bank c bank d bank e bank f bank 2 internal memory notes: ! XC800 supports memory extension of up to 1 mbyte program memory and 1 mbyte external data memory. this is accomplished by sixteen 64k bank blo cks. at any one time, only one bank of the respective memory is active. ! in case of implemented memory extension, an additional extension stack ram is added on-chip and located from 80 h to ff h . this memory is not accessible by software. ! the smallest memory space without memory extension is such that only bank 0 is available. ! in general, the data space where the corresponding code space is occupied by internal memory is reserved. ! if supported by available pins, external memory may be located at regions not occupied by internal memory. program memory : in general, #ea = 1 selects dynamic fetch from internal and external program memory; #ea = 0 selects to always fetch from external program memory instead of internal memory . data memory : external data is accessed by the movx instruction. ! this memory mapping is general for user mode. refer to respective user?s manuals for exact mappings for specific device. reserved boot rom reserved
XC800 fundamental structure user?s manual, v 0.1 1-3 2005-01 in derivatives with memory extension, an additi onal 128 bytes of memory extension stack ram is available from 80 h to ff h . access to this memory is only possible by the hardware, so the me mory is effectively transparent to the user. by defaul t after reset, the memory extension stack pointer (mexsp) points to 7f h . it is pre-incremented by call instructions and post-decrement ed by return instructions. 1.3.1 memory extension the standard amount of addr essable program or external data memory in an 8051 system is 64 kbytes. the xc8 00 core supports memory expa nsion of up to 1 mbyte and this is enabled by t he availability of a me mory management unit (mmu) and a memory extension stack. the mmu ad ds a set of memory extens ion registers (mex1, mex2, and mex3) to control access to the extend ed memory space by different addressing modes. the memory extension st ack is used by the hardware to ?push? and ?pop? values of mex1. program code is always fetch ed from the 64-kbyte block pointed to by the 4-bit current bank (cb) register bit field. it is updated from a 4-bit ne xt bank (nb) bit field upon execution of long jump (ljmp) and call instructions . cb and nb together constitute the mex1 register. the programmer simply writes the new bank nu mber to nb before a jump or call instruction. interrupt service routines ar e always executed from code in the 64-kbyte block pointed to by the interrupt bank (ib) register bit field. further, me mory constant data reads (in code space) and external data accesses ma y take place in banks other than the current bank. these banks are pointed to by the me mory constant bank pointer (mcb) and xram bank pointer (m x). these bit fields are locate d in mex2 and mex3 registers. 1.3.1.1 memory extension stack interrupts and calls in memory extension mode make use of a memory extension stack, which is updated at the same time as the standard stack. the memory extension stack is addressed using the sf r memory extension stack pointer mexsp. this read/write register provides for a sta ck depth of up to 128 bytes (bit 7 is always 0). the sfr is pre-incremente d by each call instruct ion that is executed, and post-decremented by return instru ctions. mexsp is by default reset to 7f h so that the first increment selects the bottom of the st ack. no indication of stack overflow is provided. 1.3.1.2 memory extension effects the following instructions can change the 64-kbyte bloc k pointed to: movc, movx, ljmp, lcall, acall, ret, and reti.
XC800 fundamental structure user?s manual, v 0.1 1-4 v 1.0, 2005-01 relative jumps (sjmp etc.) and absolute jumps within 2-kbyte regions (ajmps), however, will in no way change the current b ank. in other words, th ese instructions do not deselect the active 64-kbyte bank block. move constant instructions (movc) movc instructions access data bytes in either the current bank (cb19 ? cb16) or a ?memory constant? bank, defined by the mc b19 ? mcb16 bit field in mex3 and mex2. the bank selection is done by the mcm bit in mex2 (mex2.7). move external data instructions (movx) movx instructions can either access data in the current bank or a ?data memory? bank, defined by the mx19 ? mx16 bi ts in mex3. the bank selectio n is done by the mxm bit in mex3 (mex3.3). long jump instructions (ljmp) when a jump to anothe r bank of the memory extension is required, the next bank bits nb19 ? nb16 in mex1 (mex1.3 ? mex1.0) must be set to the appropriate bank address before the ljmp instru ction is executed. when the ljmp is encounter ed in the code, the next bank bits (nb19 ? 16) ar e copied to the current bank bits cb19 ? cb16 in mex1 (mex1.7 ? mex1.4) and appear on address bus at the be ginning of the next program fetch cycle. note: the next bank bits (nb19 ? 16) are not changed by the jump. call instructions (lcall and acall) whenever an lcall occurs, th e mmu carries out the foll owing sequence of actions: 1. the memory extension stack pointer is incremented. 2. the mex1 register bits are made available on data bus. 3. the mexsp register bits [6:0] are made availa ble on address lines. 4. the memory extension stack read and writ e signals are set for a write operation. 5. a write is performed to the memory extension stack. 6. the next bank bits nb19 ? nb16 (mex1.3 ? mex1.0) are copied to the cb19 ? cb16 bits (mex1.7 ? mex.4). return instructions (ret and reti) on leaving a subroutine, t he mmu carries out the foll owing sequence of actions: 1. the mexsp register bi ts [6:0] are made av ailable on address. 2. the memory extension stack read and writ e signals are set for a read operation. 3. a read is performed on th e memory extension stack. 4. memory extension stack data is written to the mex1 register. 5. the memory extension stac k pointer is decremented.
XC800 fundamental structure user?s manual, v 0.1 1-5 2005-01 1.3.2 program memory up to 1 mbyte of synchronous or asynchronous internal and/or external program memory is supported. program memory extension, if suppor ted by the XC800 derivative, is accomplished with a 4-bit current bank pointer (c b). the program code is fetched from the 64-kbyte block po inted to by cb. the minimu m supported code space is therefore 64 kbytes. if the internal program memory is used, the ea (external access) pi n must be held at high level. with ea held high, the microcontroller exec utes instructions internally unless the address (program counter) is outside the range of the internal program memory. in this case, dynami c code fetch from internal and exte rnal program memory is supported if the external memory bus is av ailable on the der ivative. if the ea pin is held at low level, the microcontroller ex ecutes program code from extern al program memory, instead of from internal memory. the gener al exception is fo r accesses to addr ess ranges of the active boot rom, internal xr am and code-space da ta (e.g., data flas h), where fetch is always from the internal memory regardless of the status of ea pin. most XC800 derivatives include a section fo r boot rom code, the size of which depends on the derivative. usually, th e boot rom code is executed fi rst after reset where the boot rom is mapped starting from base address 0000 h of the code space. the boot rom code will switch the memory mapping so that before control is passed to the user code, the standard memory map (of the derivative) is active where user c ode could run starting from address 0000 h . for program memory implement ed as ram, the XC800 core supports write to program memory with the instruction movc @(dptr++),a . this is generall y supported by the XC800 derivatives for writes to internal memory only. 1.3.3 data memory the data memory space consists of internal and external memory po rtions. the internal data memory area is address ed using 8-bit address es. the external data memory and the internal xram data memory are addressable by 8-bit or 16 -bit indirect address with ?movx?, additionally with up to 4-bit for selection of exte nded memory bank (maximum 1 mbyte). 1.3.3.1 internal data memory the internal data memory is divided into two physically separate a nd distinct blocks: the 256-byte ram and the 128-byte sfr area. while the upper 128 by tes of ram and the sfr area share the same ad dress locations, they are accessed through different addressing modes. the lower 128 bytes of ram can be acce ssed through either direct or register indirect addressing while th e upper 128 bytes of ram can be accessed through register indire ct addressing only. the special fu nction registers are accessible through direct addressing.
XC800 fundamental structure user?s manual, v 0.1 1-6 v 1.0, 2005-01 the 16 bytes of ram that occupy addresses from 20 h to 2f h are bitaddressable. bit 0 of the internal data byte at 20 h has the bit address 00 h , while bit 7 of t he internal data byte at 2f h has the bit address 7f h . by default after rese t, the stack pointer po ints to address 07 h . the stack may reside anywhere in the internal ram. ram occupying direct addresses from 30 h to 7f h can be used as scratch pad. 1.3.3.2 internal data memory xram the size of the internal xr am is not fixed an d varies depending on XC800 derivative. the internal xram is mapp ed to both the external da ta space and the code space because it can be accessed using both ?movx? and ?movc? instructions. when accessed using the 8-bit mo vx instruction via register r0 or r1, the sfr xaddrh must be initialized to spec ify the upper address byte. the internal xram can be e nabled or disabled. if disabled , external data memory can be accessed in the address ra nge of the internal xram, wi th activated external data memory signals. if enab led, the external data memory signals are not generated when the internal xram is access ed. therefore, the correspondi ng ports can be used as general purpose i/o in an application where there is no acce ss to off-chip external data/ program memory. 1.3.3.3 external data memory up to 1 mbyte of synchronou s or asynchronous external da ta memory is supported. external data memory extension, if supporte d by the XC800 derivativ e, is accomplished with either the 4-bit current bank pointer (cb) or the 4- bit xram bank pointer (mx), selected by the mxm bit. the dat a is fetched from the 64-kby te block pointed to by cb or mx. some XC800 derivatives may not support external data memory. 1.3.4 registers all registers, except the prog ram counter and the four gene ral purpose register banks, reside in the sfr area. the lower 32 locations of the internal lower data ram are assigned to four banks with eight general purpose registers (gprs) each . at any one time, onl y one of these banks can be enabled by two bits in the program status word (psw): rs0 (psw.3) and rs1 (psw.4). this allows fa st context switching, which is useful when entering subroutines or interrupt service routines. the eight general purpose regist ers of the selected register bank may be accessed by re gister addressing. for indi rect addressing modes, the registers r0 and r1 are used as pointer or index register to address internal or external memory.
XC800 fundamental structure user?s manual, v 0.1 1-7 2005-01 the special functi on registers (sfrs) are mapped to the internal data space in the range 80 h to ff h . the sfrs are accessible through di rect addressing. the sfrs that are located at addresses with addres s bit 0-2 equal to 0 (addresses 80 h , 88 h , 90 h , ..., f8 h ) are bitaddressable. each bit of the bitaddressable sfrs has bit address corresponding to the sfr byte address and its position within the sfr byte. for example, bit 7 of sf r at byte address 80 h has a bit address of 87 h . the bit addresses of the sfr bits span from 80 h to ff h . as the 128-sfr range is less than the total number of registers required, register extension mechanisms ar e implemented to in crease the number of addressable sfrs. these mechani sms include: ? mapping ?paging 1.3.4.1 special function register extension by mapping sfr extension is performed at the system le vel by mapping. the sf r area is extended into two portions: the stan dard (non-mapped) sfr area and the mapped sfr area. each portion supports th e same address range 80 h to ff h , bringing the number of addressable sfrs to 256. to access sfrs in the mapp ed area, bit rmap in sfr syscon0 must be set by so ftware. the mapp ed sfr area provides the same addressing capabilities (dir ect addressing, bit addressing) as the standard sfr area. bit rmap must be cleared by so ftware to access the sfrs in the standard area. the hardware does not automatic ally clear/set the bit. syscon0 system control register 0 reset value: xxxx xxx0 b 7 6 5 4 3 2 1 0 - rmap - rw the functions of the shaded bits are not described here field bits type description rmap 0 rw special function register map control 0 the access to the st andard sfr area is enabled. 1 the access to the ma pped sfr area is enabled.
XC800 fundamental structure user?s manual, v 0.1 1-8 v 1.0, 2005-01 1.3.4.2 special function register extension by paging the number of sfrs may be further extended for some on-chip peripherals at the module level via a paging sche me. these peripherals have a built-in local sfr extension mechanism for increasing the nu mber of addressable sfrs. the control is via bit field page in the module page register mo d_page. the bit field page must be programmed before accessing t he sfr of the target module . each module may contain different number of pages an d different number of sfrs per page, depending on the requirement. besides setting the correct rmap bit value to select the standard or mapped sfr area, the us er must also ensure that a valid page is selected to access the desired sfr. the paging mechanism is illustrated in figure 1-2 . figure 1-2 sfr extension by paging if an interrupt routi ne is initiated between the page register access and the module register access, and the interr upt must access a register located in another page, the current page setting can be saved, the new one programm ed and finally, the old page setting restored. this is possible with the storage fields stx (x = 0 - 3) for the save and restore action of the current page setting, as illustrated in figure 1-3 . by indicating which sfr0 sfr1 sfrx ? ... page 0 sfr0 sfr1 sfry ? ... page 1 ? ... sfr0 sfr1 sfrz ? ... page q mod_page.page sfr address (from cpu) sfr data (to/from cpu) rw module
XC800 fundamental structure user?s manual, v 0.1 1-9 2005-01 storage register should be us ed in parallel with the ne w page value, a single write operation can: ? save the contents of page in stx be fore overwriting wi th the new value (this is done in the beginnin g of the interrupt routine to save the current page setting and program the new page number); or ? overwrite the contents of page with the cont ents of stx, ignoring the value written to the bit positions of page (this is done at the end of the interrupt routine to rest ore the previous page setting before the inte rrupt occurred) figure 1-3 storage elements for paging with this mechanism, a certain number of interrupt r outines (or other routines) can perform page changes without re ading and storing the previo usly used page information. the use of only write operati ons makes the system simple r and faster. consequently, this mechanism significantly improves the performance of short interrupt routines. the page register has th e following definition: mod_page page register for module mod reset value: 00 h 7 6 5 4 3 2 1 0 op stnr 0 page w w r rw page st0 st1 st2 st3 value update from cpu stnr
XC800 fundamental structure user?s manual, v 0.1 1-10 v 1.0, 2005-01 field bits type description page [2:0] rw page bits when written, the value indicates the new page. when read, the value indica tes the currently active page. stnr [5:4] w storage number this number indicates whic h storage bit field is the target of the operation defined by bit field op. if op = 10 b , the contents of page are sa ved in stx before being overwritten with the new value. if op = 11 b , the contents of page ar e overwritten by the contents of stx. the value written to the bit positions of page is ignored. 00 st0 is selected. 01 st1 is selected. 10 st2 is selected. 11 st3 is selected. op [7:6] w operation 0x manual page mode. the value of stnr is ignored and page is directly written. 10 new page programming with automatic page saving. the value writte n to the bit field page is stored. in parallel, th e previous contents of page are saved in the storage bit field stx indicated by stnr. 11 automatic restore p age action. the value written to the bit field page is ignored and instead, page is overwri tten by the contents of the storage bit fiel d stx indicated by stnr. 0 3 r reserved returns 0 if re ad; should be wr itten with 0.
XC800 fundamental structure user?s manual, v 0.1 1-11 2005-01 1.4 bit protection scheme the bit protection scheme prevents direct software writing of selected bits (i.e., protected bits) by the passwd register. wh en the bit field mode is 11 b , writing 10011 b to the bit field pass opens access to writing of all pr otected bits and writing 10101 b to the bit field pass closes access to writin g of all protected bits. note that access is opened for maximum 32 cclks if the ?c lose access? password is not written. if ?open access? password is written again before the end of 32 cclk cycles, there will be a recount of 32 cclk cycles. the bits or bit fields that are protect ed may differ for the XC800 derivatives. passwd password register reset value: 07 h 7 6 5 4 3 2 1 0 pass protect _s mode wh rh rw field bits type description mode [1:0] rw bit-protection sche me control bit 00 scheme disabled 11 scheme enabled (default) others: scheme enabled these two bits cannot be written direct ly. to change the value between 11 b and 00 b , the bit field pass must be written with 11000 b , only then will the mode[1:0] be registered. protect_s 2 rh bit-protection signal status bit this bit shows the stat us of the protection. 0 software is able to write to all protected bits. 1 software is unable to write to any protected bits. pass [7:3] wh password bits the bit-protection scheme recognizes only three patterns. 11000 b enables writing of the bit field mode. 10011 b opens access to writing of all protected bits. 10101 b closes access to writing of all protected bits.
XC800 cpu architecture user?s manual, v 0.1 2-1 2005-01 2 cpu architecture figure 2-1 depicts the typical architecture of an XC800 family microcontroller. it includes the main functional blocks and standard units. the units represented by dotted boxes may not be available, de pending on the deri vative; these includ e peripheral units and external memory bus. memory sizes va ry depending on the xc 800 microcontroller derivative. figure 2-1 typical architecture of XC800 family microcontroller the cpu functional blocks are shown in figure 2-2 . the cpu consists mainly of the instruction decoder, the arithmetic section, the program control section, the access control section, and the inte rrupt controller. th e cpu also provides modes for power saving. the instruction decoder decode s each instruction and accord ingly generates the internal signals required to co ntrol the functions of the individ ual units within the cpu. these internal signals have an effect on the source and dest ination of signal transfers and control the alu processing. adc ports ccu6 timer 2 ssc watchdog timer boot rom internal data ram xram flash or rom XC800 core t0 & t1 uart system control unit v aref v agnd osc & pll xtal1 xtal2 internal bus v ddp v ssp v ddc v ssc reset external data memory external code memory can mdu 1) ocds: on-chip debug support standard jtag i/o cordic ocds 1)
XC800 cpu architecture user?s manual, v 0.1 2-2 2005-01 figure 2-2 XC800 core block diagram the arithmetic section of the processor performs extens ive data manipulation and consists of the arithmetic/logic unit (alu), a register, b register , and psw register. the alu accepts 8-bit data words from one or two sources, and generates an 8-bit result under the control of the instru ction decoder. the alu performs both arithmetic and logic operations. arithmetic operati ons include add, subtract, mu ltiply, divide, increment, decrement, bcd-decimal-add-ad just, and compare. logic operations include and, or, exclusive or, complement, and rotate (right, left, or swap nibble (left four)). also included is a boolean unit pe rforming the bit operations su ch as set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set-and- clear, and move to/from carry. the alu can perform the bit operations of logical and or logical or bet ween any addressable bit (or its complement) and the carry flag, and place the new result in the carry flag. the program control section cont rols the sequence in which the instructions stored in program memory are executed. the 16-bit program counter (pc) holds the address of register interface alu uart core sfrs 16-bit registers & memory interface opcode decoder state machine & power saving interrupt controller multiplier / divider opcode & immediate registers timers / counters internal data memory external sfrs external data memory program memory f cclk memory wait reset legacy external interrupts (ien0, ien1) external interrupts non-maskable interrupt
XC800 cpu architecture user?s manual, v 0.1 2-3 2005-01 the next instruction to be ex ecuted. the conditional branch logic enables internal and external events to the processor to cause a change in the prog ram execution sequence. the access control unit is responsible for the selection of the on-chip memory resources. the interrupt requests from the peripheral units are hand led by the interrupt controller unit.
XC800 cpu architecture user?s manual, v 0.1 2-4 2005-01 2.1 cpu register description the cpu registers occupy direct internal da ta memory space locations in the range 80 h to ff h . 2.1.1 stack pointer (sp) the sp register contains the stack pointer. the stack pointer is used to load the program counter into internal data memory during lcall and acall instructions, and to retrieve the program coun ter from memory during ret an d reti instructions. data may also be saved on or retr ieved from the stack using push and pop instructions. instructions that use the stac k automatically pre-increment or post-decrement the stack pointer so that the stac k pointer always points to the last byte written to the stack, i.e. the top of the stack. on reset, t he stack pointer is reset to 07 h . this causes the stack to begin at a location = 08 h above register bank zero. the sp can be read or written under software control. the programme r must ensure that the location and size of the stack in internal data memory do not interfere with other application data. 2.1.2 data pointer (dptr) the data pointer (dptr) is stored in re gisters dpl (data poin ter low byte) and dph (data pointer high byte) to form 16-bit addresses for exte rnal data memory accesses (movx a,@dptr and movx @dptr,a), for program byte moves (movc a,@a+dptr), and for indi rect program jumps (jmp @a+dptr). two true 16-bit ope rations are allowed on the da ta pointer: load immediate (mov dptr,#data) and increment (inc dptr). the cpu can support up to 8 data pointers. this helps programming in high level languages, which may requi re the storing of data in large external data memory portions. selection of the active data poin ter is done via t he sfr eo (see section 2.1.6 ). the number of data pointers available is specific to the XC800 derivative. 2.1.3 accumulator (acc) this register is an operand for most alu operations. acc is the symbol for the accumulator register. the mn emonics for accumulator-speci fic instructions, however, refer to the accumulator simply as ?a?. 2.1.4 b register the b register is used during multiply an d divide operations to provide the second operand. for other instructio ns, it can be treated as ano ther scratch pad register.
XC800 cpu architecture user?s manual, v 0.1 2-5 2005-01 2.1.5 program status word the program status word (psw ) contains several status bi ts that reflect the current state of the cpu. psw program status word re gister reset value: 00 h 7 6 5 4 3 2 1 0 cy ac f0 rs1 rs0 ov f1 p rw rwh rwh rw rw rwh rwh rh field bits type description p 0 rh parity flag set/cleared by hardware a fter each instruction to indicate an odd/eve n number of ?one ? bits in the accumulator, i.e., even parity. f1 1 rwh general purpose flag ov 2 rwh overflow flag used by arithmetic instructions rs0 rs1 3 4 rw register bank select these bits are used to select one of the four register banks. f0 5 rwh general purpose flag ac 6 rwh auxiliary carry flag used by instructions th at execute bcd operations cy 7 rw carry flag used by arithmetic instructions rs1 rs0 function 0 0 bank 0 selected, data address 00 h -07 h 0 1 bank 1 selected, data address 08 h -0f h 1 0 bank 2 selected, data address 10 h -17 h 1 1 bank 3 selected, data address 18 h -1f h
XC800 cpu architecture user?s manual, v 0.1 2-6 2005-01 2.1.6 extended operation register (eo) the eo register has two functions. one function is to select the acti ve data pointer where the derivative has multip le data pointers. the other functi on is to select the instruction executed on opcode a5 h . the active instru ction is either trap or movc @(dptr++),a . eo extended operation re gister reset value: 00 h 7 6 5 4 3 2 1 0 0 trap_en 0 dpsel r rw r rw field bits type description dpsel [2:0] rw data pointer select 000 dptr0 selected 001 dptr1 selected (if available) 010 dptr2 selected (if available) 011 dptr3 selected (if available) 100 dptr4 selected (if available) 101 dptr5 selected (if available) 110 dptr6 selected (if available) 111 dptr7 selected (if available) trap_en 4 rw trap enable 0 select movc @(dptr++),a 1 select software trap instruction 0 3, [7:5] r reserved returns 0 if re ad; should be wr itten with 0.
XC800 cpu architecture user?s manual, v 0.1 2-7 2005-01 2.1.7 memory extension registers these registers support the me mory extension feature, whic h may not be available on certain XC800 microcontroller derivatives. mex1 memory extension register 1 reset value: 00 h 7 6 5 4 3 2 1 0 cb[19:16] nb[19:16] rh rw field bits type description nb[19:16] [3:0] rw next bank number cb[19:16] [7:4] rh current bank number mex2 memory extension register 2 reset value: 00 h 7 6 5 4 3 2 1 0 mcm mcb[18:16] ib[19:16] rw rw rw field bits type description ib[19:16] [3:0] rw interrupt bank number mcb[18:16] [6:4] rw memory constant bank number (with mex3.7) mcm 7 rw memory constant mode 0 movc access data in the current bank 1 movc access data in the memory constant bank
XC800 cpu architecture user?s manual, v 0.1 2-8 2005-01 mex3 memory extension register 3 reset value: 00 h 7 6 5 4 3 2 1 0 mcb19 0 mx19 mxm mx[18:16] rw r rw rw rw field bits type description mx[19:16] [2:0], 4 rw xram bank number mxm 3 rw xram bank selector 0 movx access data in the current bank 1 movx access data in the memory xram bank mcb19 7 rw memory constant bank number msb 0 [6:5] r reserved returns 0 if re ad; should be wr itten with 0. mexsp memory extension stack pointe r register reset value: 7f h 7 6 5 4 3 2 1 0 0 mxsp r rw field bits type description mxsp [6:0] rw memory extension stack pointer it provides for a stack depth of up to 128 bytes. it is pre-incremented by call instructions and post- decremented by retu rn instructions. 0 7 r reserved returns 0 if re ad; should be wr itten with 0.
XC800 cpu architecture user?s manual, v 0.1 2-9 2005-01 2.1.8 power control register (pcon) the XC800 cpu has two power saving modes: idle mode a nd power-down mo de. in idle mode, the clock to the cpu is disabled wh ile other peripherals may continue to run (possibly at lower frequency). in power-dow n mode, the clock to the entire cpu is stopped. pcon power control regist er reset value: 00 h 7 6 5 4 3 2 1 0 smod 0 gf1 gf0 0 idle rw r rw rw r rw field bits type description idle 0 rw idle mode enable 0 do not enter idle mode 1 enter idle mode gf0 2 rw general purpose flag bit 0 gf1 3 rw general purpose flag bit 1 smod 7 rw double baud rate enable 0 do not double the baud rate of serial interface in mode 2 1 double baud rate of seri al interface in mode 2 0 1, [6:4] r reserved returns 0 if re ad; should be wr itten with 0.
XC800 cpu architecture user?s manual, v 0.1 2-10 2005-01 2.1.9 uart registers the uart uses two sfrs, scon and sbuf. scon is the control register, while sbuf is the data register. the seri al port control and status re gister is the sfr scon. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8) , and the serial port in terrupt bits (ti and ri). sbuf is the receive and transmit buffer of the serial interface. writ ing to sbuf loads the transmit register and initiate s transmission. sbuf is read to access the received data from the receive register. the two paths are independent and sup ports full duplex operation. sbuf serial data buffer reset value: 00 h 7 6 5 4 3 2 1 0 val rwh field bits type description val [7:0] rwh serial interface buffer register scon serial channel control register reset value: 00 h 7 6 5 4 3 2 1 0 sm0 sm1 sm2 ren tb8 rb8 ti ri rw rw rw rw rw rwh rwh rwh field bits type description ri 0 rwh receive interrupt flag this is set by hardware at the end of the 8th bit in mode 0, or at the half poin t of the stop bit in modes 1, 2, and 3. must be cleared by software. ti 1 rwh transmit interrupt flag this is set by hardware at the end of the 8th bit in mode 0, or at the beginni ng of the stop bit in modes 1, 2, and 3. must be cleared by software.
XC800 cpu architecture user?s manual, v 0.1 2-11 2005-01 rb8 2 rwh serial port receiver bit 9 in modes 2 and 3, this is the 9th data bit received. in mode 1, if sm2 = 0, this is the stop bit received. in mode 0, rb8 is not used. tb8 3 rw serial port transmitter bit 9 in modes 2 and 3, this is the 9th data bit sent. ren 4 rw enable receiver of serial port 0 serial recepti on is disabled 1 serial recepti on is enabled sm2 5 rw enable serial port multiprocessor communication in modes 2 and 3 in mode 2 or 3, if sm2 is set to 1, ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 is set to 1, ri will no t be activated if a valid stop bit (r b8) was not received. in mode 0, sm2 should be set to 0. sm1 sm0 6 7 rw serial port operat ing mode selection field bits type description sm0 sm1 selected operating mode 0 0 mode 0: 8-bit shif t register, fixed baud rate = f pclk /2 0 1 mode 1: 8-bit uart, variable baud rate 1 0 mode 2: 9-bit ua rt, fixed baud rate (f pclk /32 or f pclk /64) 1 1 mode 3: 9-bit uart, variable baud rate
XC800 cpu architecture user?s manual, v 0.1 2-12 2005-01 2.1.10 timer/counter registers two 16-bit timers, timer 0 and timer 1, are available in the XC800 core. the sfr tcon controls the r unning of the timers and generating of interrupts, while sfr tmod sets the oper ating modes of the timers. the ti mer/counter values are stored in two pairs of 8-bit register s: tl0, th0 and tl1, th1. tcon timer control register reset value: 00 h 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 rwh rw rwh rw rw rw rw rw field bits type description tr0 4 rw timer 0 run control 0 timer is halted 1 timer runs tf0 5 rwh timer 0 overflow flag set by hardware when timer 0 overflows. cleared by hardware when the proc essor calls the interrupt service routine. tr1 6 rw timer 1 run control 1) 0 timer is halted 1 timer runs 1) also affects th0 if timer 0 operates in mode 3. tf1 7 rwh timer 1 overflow flag set by hardware when timer 1 2) overflows. cleared by hardware when the proc essor calls the interrupt service routine. 2) tf1 is set by th0 instead if timer 0 operates in mode 3. the functions of the shaded bits are not described here
XC800 cpu architecture user?s manual, v 0.1 2-13 2005-01 tmod timer mode regist er reset value: 00 h 7 6 5 4 3 2 1 0 gate1 ct1 t1m gate0 ct0 t0m rw rw rw rw rw rw field bits type description t0m[1:0], t1m[1:0] [1:0], [5:4] rw mode select bits ct0, ct1 2, 6 rw counter selection for timer x 0 timer mode (input from internal s ystem clock) 1 counter mode (input from tx input pin) gate0, gate1 3, 7 rw timer x gating control 0timer x will only run if tcon.trx = 1 (software control) 1timer x will only run if nint x pin = 0 (hardware control) and tcon.trx is set t0m/t1m [1:0] function 00 13-bit timer thx operates as 8-bit timer/counter tlx is a 5-bit prescaler 01 16-bit timer thx and tlx are cascaded 10 8-bit auto-reload timer thx holds the relo ad value which is reloaded into tlx each time it overflow 11 timer 0: timer 0 is divided into two parts. tl0 is an 8-bit timer controlled by the standard timer 0 co ntrol bits, and th0 is the other 8-bit timer controlled by the standard timer 1 control bits. timer 1: th1 and tl1 are he ld (timer 1 is stopped).
XC800 cpu architecture user?s manual, v 0.1 2-14 2005-01 2.1.11 interrupt registers each interrupt for a peripheral (if available for the derivative ) can be indivi dually enabled or disabled by setting or clearing the corre sponding bit in the bi taddressable interrupt enable registers ien0 and ien1 . register ien0 also contai ns the global enable/disable bit (ea), which can be cleared to disable all interrupts at once . the non- maskable interrupt (nmi) is always enabled. after reset, the enable bits of ien0 and ien1 are cleared to 0. this impl ies that the corresponding interrupt s are disabled. ien0 interrupt enable regist er 0 reset value: 00 h 7 6 5 4 3 2 1 0 ea 0 et2 es et1 ex1 et0 ex0 rw r rw rw rw rw rw rw field bits type description ex0 0 rw enable external interrupt 0 0 external interrupt 0 is disabled. 1 external interrupt 0 is enabled. et0 1 rw enable timer 0 overflow interrupt 0 timer 0 overflow in terrupt is disabled. 1 timer 0 overflow in terrupt is enabled. ex1 2 rw enable external interrupt 1 0 external interrupt 1 is disabled. 1 external interrupt 1 is enabled. et1 3 rw enable timer 1 overflow interrupt 0 timer 1 overflow in terrupt is disabled. 1 timer 1 overflow in terrupt is enabled. es 4 rw enable serial port interrupt 0 serial port interru pt is disabled. 1 serial port interrupt is enabled. et2 5 rw enable timer 2 interrupt 0 timer 2 interrupt is disabled. 1 timer 2 interru pt is enabled.
XC800 cpu architecture user?s manual, v 0.1 2-15 2005-01 the interrupt enable bi ts of ien1 are used to enable or disable the corresponding interrupts. the assignment of these bits depends on which pe ripheral set is available on the derivative. each interrupt source can be individually programme d to one of the four priority levels available via the correspondi ng ip, iph or ip1, iph1 registers. ip and ip1 are bitaddressable, but not iph and iph1. ea 7 rw enable/disable all interrupts 0 no interrupt will be acknowledged. 1 each interrupt source is individually enabled or disabled by setting or cleari ng its enable bit. 0 6 r reserved returns 0 if read; shou ld be written with 0. ien1 interrupt enable regist er 1 reset value: 00 h 7 6 5 4 3 2 1 0 ei13 ei12 ei11 ei10 ei9 ei8 ei7 ei6 rw rw rw rw rw rw rw rw field bits type description eix (x = 6 - 13) [7:0] rw extended interrupt enable 0 interrupt is disabled. 1 interrupt is enabled. ip interrupt priority re gister reset value: 00 h 7 6 5 4 3 2 1 0 0 pt2 ps pt1 px1 pt0 px0 r rw rw rw rw rw rw field bits type description
XC800 cpu architecture user?s manual, v 0.1 2-16 2005-01 the respective bit fields of th e interrupt priority registers to gether select one of the four levels of priority shown in table 2-1 . note: the nmi always takes precede nce over all other interrupts. iph interrupt priority high r egister reset value: xx00 0000 b 7 6 5 4 3 2 1 0 0 pt2h psh pt1h px1h pt0h px0h r rw rw rw rw rw rw field bits type description px0, px0h 0 rw priority level for ex ternal interrupt 0 pt0, pt0h 1 rw priority level for time r 0 overflow interrupt px1, px1h 2 rw priority level for ex ternal interrupt 1 pt1, pt1h 3 rw priority level for time r 1 overflow interrupt ps, psh 4 rw priority level for se rial port interrupt pt2, pt2h 5 rw priority level for timer 2 interrupt 0 [7:6] r reserved returns 0 if read; shou ld be written with 0. table 2-1 interrupt priority level selection iph.x / iph1.x ip.x / ip1.x priority level 0 0 level 0 (lowest) 0 1 level 1 1 0 level 2 1 1 level 3 (highest)
XC800 cpu architecture user?s manual, v 0.1 2-17 2005-01 four bits are available in tcon to control and flag the external interrupts. tcon timer control regist er reset value: 00 h 7 6 5 4 3 2 1 0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 rwh rw rwh rw rwh rw rwh rw the functions of the shaded bits are not described here field bits type description it0 0 rw external interrupt 0 le vel/edge trig ger control flag 0 low level triggered external interrupt 0 is selected. 1 falling edge triggered external interrupt 0 is selected. ie0 1 rwh external interrupt 0 request flag set by hardware when extern al interrupt 0 edge is detected. cleared by hardware when the processor vectors to interrupt routine. it1 2 rw external interrupt 1 le vel/edge trig ger control flag 0 low level triggered external interrupt 1 is selected. 1 falling edge triggered external interrupt 1 is selected. ie1 3 rwh external interrupt 1 request flag set by hardware when extern al interrupt 1 edge is detected. cleared by hardware when the processor vectors to interrupt routine.
XC800 cpu architecture user?s manual, v 0.1 2-18 2005-01 2.2 on-chip debug support concept the XC800 microcontrollers have an on-chip debug suppor t (ocds) unit that provides basic functionality to support software devel opment and debugging of the XC800-based systems. the debug func tionality is usually en abled after the device has been started in ocds mode. the debug concept is based on the interaction betw een the ocds ha rdware and a dedicated software (monitor program) whic h is usually located in the boot rom. standard interface such as th e jtag or uart is used to communicate with an external host (a debugger). an overview of the debug interfaces is shown in figure 2-3 . figure 2-3 XC800 ocds block diagram ? a monitor mode cont rol (mmc) block at the center of the ocds system brings together control sig nals and suppor ts the overall functionality ? mmc communicates with the XC800 core prim arily via the debug interface, and also receives reset an d clock signals ? after processing memory a ddress and control si gnals from the core, mmc provides proper access to the dedi cated memories: a m onitor rom (holding the code) and a monitor ram (for work-d ata and monitor-stack) jtag module moni tor & bootstrap loader control line jtag memory control unit use r program memory uart XC800 prog & iram addresses txd rxd debug interface reset clock tms tck tdi tdo tck tdi tdo control uart memory cont rol alternate debug interface primary de bug interface system co ntr ol un i t ocds interrupt boot/ moni tor rom moni t or ram use r internal ram reset cpu reset cl ock evr re set prog data monitor mode control nmi report flash (program memory) cont rol memory configurat ion - parts of ocds
XC800 cpu architecture user?s manual, v 0.1 2-19 2005-01 ? two interfaces can be used to access the ocds system: ? jtag as a primary channel; dedicated excl usively to test and debug activities and is not normally used in an application ? uart as an alternative channel; it has the advantage of need ing fewer pins, but causes a loss (at least partially) to th e standard serial inte rface while debugging ? a dedicated pin is used as external configurat ion and control for both the debugging and bootstrap-loading. the on-chip debug concept is based on the generat ion and detection of debug events and the correspondi ng debug actions. ? debug events: ? hardware breakpoints ? software breakpoints ? external breaks ? debug event action s (non-exclusive): ? call the monitor program: once in deb ug mode and with t he monitor running, access for read and write of all of the (non-protected ) system resources and data can be communicated through an exter nal debugger. ? activate the mbc pin
XC800 cpu architecture user?s manual, v 0.1 2-20 2005-01 2.3 basic interrupt handling 2.3.1 interrupt source and vector address each interrupt source has an associated in terrupt vector address. this vector is accessed to serv ice the corresponding interrupt sour ce. the assi gnment of the XC800 interrupt sources is summarized in table 2-2 .the extended interru pts are generally assigned to on-chip periphe rals, which vary depending on the XC800 derivative. table 2-2 interrupt vector addresses 2.3.2 interrupt handling the interrupt flags are sampled at phase 2 in each machine cycle. the sampled flags are polled during the followi ng machine cycle. if one of the flags was in a set condition at phase 2 of the preceding cy cle, the polling cycle will fi nd it and the interrupt system will generate a lcall to the appropriate service routine, provided this hardware- generated lcall is not blocked by any of th e following conditions: 1. an interrupt of equal or higher priority is already in progress. 2. the current (polling) cycle is not in the final cycle of the instruction in progress. interrupt source vector address interrupt sources xintr0 0003 h external interrupt 0 xintr1 000b h timer 0 xintr2 0013 h external interrupt 1 xintr3 001b h timer 1 xintr4 0023 h uart xintr5 002b h extended interrupt 5 (timer 2) xintr6 0033 h extended interrupt 6 xintr7 003b h extended interrupt 7 xintr8 0043 h extended interrupt 8 xintr9 004b h extended interrupt 9 xintr10 0053 h extended interrupt 10 xintr11 005b h extended interrupt 11 xintr12 0063 h extended interrupt 12 xintr13 006b h extended interrupt 13 nmi 0073 h non-maskable interrupt
XC800 cpu architecture user?s manual, v 0.1 2-21 2005-01 3. the instruction in progress is reti or any write access to registers ien0/ien1 or ip,iph/ip1,ip1h. any of these three conditions will block th e generation of the lc all to the interrupt service routine. conditi on 2 ensures that the instructi on in progress is completed before vectoring to any service routine. condition 3 ensures that if the instruction in progress is reti or any write access to registers ien0/ien1 or ip,iph/ip1,ip1h, then at least one more instruction will be executed before any interrupt is vectored to; this delay guarantees that cha nges in the interrupt status can be observed by the cpu. the polling cycle is re peated with each ma chine cycle, and the values polled are the values that were present at phase 2 of the previous machine cycle. note that if any interrupt flag is active but no t responded to for on e of the conditions already mentioned, or if the flag is no longer active when th e blocking condition is removed, the denied interrupt will not be serviced . in other words, the fact th at the interrupt flag was once active but not servic ed is not remembered. every poll ing cycle interrogates only the pending interrupt requests. the processor acknowledges an interrupt request by exec uting a hardwa re generated lcall to the appropriate servicin g routine. in some cases, ha rdware also clears the flag that generated the interrupt, while in other cases, the flag must be cleared by the user?s software. the hardware -generated lcall pushe s the contents of the program counter onto the stack (but it does not save the psw) and reloads the prog ram counter with an address that depends on the source of the inte rrupt being vectored to. execution proceeds from that location until the reti inst ruction is encountered. the reti instruction informs the proc essor that the interrupt routin e is no longer in progress, then pops the two top bytes fr om the stack and reloads t he program counter. execution of the interrupted program continues from the point where it was stopped. note that the reti instruction is important because it informs the processo r that the program has left the current interrupt priority level. a simple ret instruction would also have returned execution to the interrupted program; but, it would have left the in terrupt control system on the assumption that an interrupt was still in progress. in this case, no interrupt of the same or lower priority le vel would be acknowledged. 2.4 interrupt response time if an external interrupt is re cognized, its correspon ding request flag is set at phase 2 in every machine cycle. the value is not polled by the circuitry until the next machine cycle. if the request is active and conditions are right for it to be ac knowledged, a hardware subroutine call to the reques ted service routine will be th e next instruction to be executed. the call itself ta kes two machine cycle s. thus, a minimum of three complete machine cycles will elapse between activation of the interrupt reque st and the beginning of execution of the first instruction of the service routine. a longer response time would be obtained if the reques t is blocked by one of the three previously listed conditions. if an interrupt of equa l or higher priority is already in progress, the a dditional wait time will
XC800 cpu architecture user?s manual, v 0.1 2-22 2005-01 depend on the nature of the other interrupt's service routine. if the instru ction in progress is not in its final cycl e, the additional wait time cannot be more than three machine cycles since the longest instructions (mul and div) are only four machine cycles long. if the instruction in progress is reti or a write access to register s ien0, ien1 or ip(h), ip1(h), the additional wait time cannot be more than five cycles (a maximum of one more machine cycle to complete th e instruction in progress, pl us four machine cycles to complete the next instruction, if the instruction is mul or div). thus, in a single interrupt system without wait states, th e response time is between th ree and nine ma chine cycles. 2.5 service order a low-priority interrupt can be interrupted by a high-priorit y interrupt, but not by another interrupt of the same or lower priority. an interrupt of the highest priority cannot be interrupted by any ot her interrupt source. if two or more requests of different priori ty levels are received simultaneously, the request of the highest priority is serviced first. if requests of the same priority are received simultaneously , an internal pollin g sequence determines which request is serviced first. thus, within each priority level there is a second priority structure determined by the polling sequence as shown in table 2-3 . the extended interrupts that are applicable, va ry depending on the XC800 derivative. table 2-3 priority structure within interrupt level source level non-maskable interrupt (nmi) (highest) external interrupt 0 1 timer 0 interrupt 2 external interrupt 1 3 timer 1 interrupt 4 uart interrupt 5 extended interrupt 5 (timer 2) 6 extended interrupt 6 7 extended interrupt 7 8 extended interrupt 8 9 extended interrupt 9 10 extended interrupt 10 11 extended interrupt 11 12
XC800 cpu architecture user?s manual, v 0.1 2-23 2005-01 extended interrupt 12 13 extended interrupt 13 14 table 2-3 priority structur e within interrupt level (cont?d) source level
XC800 cpu timing user?s manual, v 0.1 3-1 2005-01 3cpu timing 3.1 instruction timing a cpu machine cycle comprises two input cl ock periods, referred to as phase 1 (p1) and phase 2 (p2), that corresp ond to two different cpu stat es. a cpu state within an instruction is referenced by the machine cy cle and state number, e.g., c2p1 means the first clock period within mach ine cycle 2. memory access ta kes place during one or both phases of the machine cycle. sf r writes occur only at the end of p2. instructions are 1, 2, or 3 bytes long and can ta ke 1, 2 or 4 mach ine cycles to exec ute. registers are generally updated an d the next opcode pre-fetched at th e end of p2 of the last machine cycle for the curre nt instruction. the XC800 core supports access to slow (inter nal) memory by using wait state(s). each wait state lasts one machine c ycle. for example, in case of a memory requi ring one wait state, the access time is increased by on e machine cycle after every byte of opcode/ operand fetched. figure 3-1 shows the fetch/execute timing relat ed to the internal states and phases. execution of an instruction oc curs at c1p1. for a 2-byte in struction, the second reading starts at c1p1. figure 3-1 (a) shows two timing diagra ms for a 1-by te, 1-cycle (1 machine cycle) instruction. the first diagra m shows the instruction being executed within one machine cycle since the opcode (c1p2) is fetched from a memory without wait state. the second diagram shows the corre sponding states of th e same instruction being executed over two machine cycles (ins truction time extended), with o ne wait state inserted for opcode fetching from a slower memory. figure 3-1 (b) shows two timing diagra ms for a 2-by te, 1-cycle (1 machine cycle) instruction. the first diagra m shows the instruction being executed within one machine cycle since the second byte (c1p1) and the opcode (c1p2) are fetched from a memory without wait state. the seco nd diagram shows the corres ponding states of the same instruction being executed over three machi ne cycles (instruction time extended), with one wait state inserted for each access to the slow memory (two wait states inserted in total). figure 3-1 (c) shows two timing diagrams of a 1-byte, 2-cycle (2 machine cycle) instruction. the first diagra m shows the instruction being executed over two machine cycles with the opcode (c2p2) fetched from a memory with out wait state. the second diagram shows the corre sponding states of th e same instruction being executed over three machine cycles (instructi on time extended), wi th one wait state inserted for opcode fetching from the slow memory.
XC800 cpu timing user?s manual, v 0.1 3-2 2005-01 figure 3-1 cpu instruction timing the time taken for each instruction includes: ? decoding/executing the fetched opcode ? fetching the operand/s (for instructions > 1 byte) ? fetching the first byte (o pcode) of the next instruct ion (due to cpu pipeline) note: the XC800 cpu fetches t he opcode of the next inst ruction while executing the current instruction. even with one wait state inse rted for each byte of operan d/opcode fetched, the XC800 cpu executes instructions faster than t he standard 8051 processor by a factor of between two (e.g., 2-byte, 1-cycle instructions ) to six (e.g., 1-byte, 4-cycle instructions). f cclk c1p1 c1p2 read next opcode (without wait state) c1p1 c1p2 (a) 1-byte, 1-cycle instruction, e.g. inc a wait wait read next opcode (one wait state) c1p1 c1p2 read next opcode (without wait state) c1p1 c1p2 (b) 2-byte, 1-cycle instruction, e.g. add a, #data wait wait read next opcode (one wait state) read 2 nd byte (without wait state) wait wait read 2 nd byte (one wait state) c1p1 c1p2 c1p1 c1p2 wait c2p1 c2p2 read next opcode (without wait state) c2p1 wait c2p2 read next opcode (one wait state) (c) 1-byte, 2-cycle instruction, e.g. movx next instruction next instruction next instruction next instruction next instruction next instruction
XC800 cpu timing user?s manual, v 0.1 3-3 2005-01 3.2 accessing external memory there are two types of external memory accesses: accesses to external program memory and accesses to exte rnal data memory. accesses to external program memory use the signal psen as the read strobe, while access es to external data memory use the rd or wr to read or write the memory. dependi ng on the derivative that supports external memory accessing, address (ax) and data (d[7:0]) lines ma y be multiplexed as alternate function of the available ports. 3.2.1 accessing external program memory external program memory is genera lly accessed under two conditions: ? whenever ea is active (low), or ? whenever ea is inactive (high) and the progra m counter (pc) contains an address outside the range of the internal code memories. fetches from external program memory use ad dress bus width of 16 bits, and up to 20 bits if memory extension is supported (uppermost 4 bits for bank sele ction). these address pins are the alternate function of the corre sponding ports, and when the cpu is executing from external program memory, shou ld never be used for other alternate port functions. figure 3-2 shows the timing of the extern al program memory access cycle. figure 3-2 external progra m memory fetches cclk ax d[7:0] psen program 2) add. a+1 or a+2 program add. a program 1) add. a+1 cxp2 c1p1 c1p2 cyp2 d a+1 valid 1) address discarded if 1-byte instruction. in this case, no valid code is fetched on data bus. 2) address a+1 valid again if previously discarded. corresponding code d a+1 will be fetched. d a+1/2 valid d a valid
XC800 cpu timing user?s manual, v 0.1 3-4 2005-01 3.2.2 accessing external data memory external data memory may ge nerally be accessed only if the corresp onding address is not occupied by internal prog ram memory in the code space. the access to external data memo ry uses address bits 17 up to 20 (if available) for bank selection. within each bank of external data memory, acce ss can be via either a 16-bit address ( movx @dptr ) or an 8-bit address ( movx @r i ). if an 8-bit addressing mode is used, any output port pins can be used to ou tput high-order addres s bits. alternatively, the contents of the corresponding port sfr of the hi gh-byte address pins may be initialised to hold the high-byt e address on the pi ns during the extern al memory access. these pins are therefore used to page the current active bank (selected by mex1.cbx or mex3.mxx) of external memory by defining the upper address byte. in a read cycle, the incomi ng byte is accepted just before the read strobe rd is deactivated. figure 3-3 shows the timing of the external data memory re ad cycle. this timing assumes only data access on the external interface. figure 3-3 external data memory read cycle c1p1 c1p2 c2p1 c2p2 c1p1 movx next instructi on valid data address cclk rd ax d[7:0]
XC800 cpu timing user?s manual, v 0.1 3-5 2005-01 in a write cycle, the data byte to be wr itten appears at the pins before wr is activated, and remains there after wr is deactivated. figure 3-4 shows the timing of the external data memory write cycle. this timing assumes multiplexed program fetch and da ta access on the external interface. figure 3-4 external data memory write cycle c1p1 c1p2 c2p1 c2p2 c1p1 movx next instructi on cclk rd ax d[7:0] wr psen valid data data address prog. add. prog. add. prog. add. prog. add. (di scarded)
XC800 instruction set user?s manual, v 0.1 4-1 2005-01 4 instruction set the XC800 8-bit microcontroller family instruct ion set includes the 11 1 instructions of the standard 8051, plus 2 a dditional instructions, movc @(dptr++),a and trap, which are multiplexed and selected through the sp ecial function register (sfr) eo. out of the 113 instructions, 51 ar e single-byte, 46 are two-by te and 16 are three-byte. the instruction opcode format consists of a function mn emonic that is usually followed by a ?destination, source? operand field. this field specifies the data type and addressing method(s) to be used. 4.1 addressing modes the XC800 uses five ge neral addressing modes: ?register ?direct ? immediate ? register indirect ? base register plus in dex-register indirect table 4-1 summarizes the memory space(s) that may be accessed by each addressing mode. register addressing register addressing accesses the eight working registers (r0 - r7) of the selected register bank. the least signif icant bit of the instruction op code indicates which register is to be used. some instructio ns only operate on specific r egisters such as acc (a), b, dptr, or on the bit cy (the boolean accumulator). table 4-1 addressing mode and associated memory space addressing mode associated me mory space register addressing r0 through r7 of se lected register bank, acc, b, cy (bit), dptr direct addressing lower 128 bytes of in ternal ram, special function registers immediate addressing program memory register indirect addressing internal ram (@r1, @r0, sp), external data memory (@r1, @r0, @dptr) base register plus in dex register addressing program memory (@a + dptr, @a + pc) register addressing r0 through r7 of se lected register bank, acc, b, cy (bit), dptr
XC800 instruction set user?s manual, v 0.1 4-2 2005-01 direct addressing direct addressing is the only method of accessing the sfrs. the lower 128 bytes of internal ram are also directly addressable. in direct addressing, th e operand is specified by an 8-bit address field. immediate addressing immediate addressing allows co nstants to be part of the in struction in program memory. these instructions are 2 or more bytes long. register indirect addressing register indirect addres sing uses the contents of either r0 or r1 (i n the selected register bank) as a pointer to locations in a 256-byte block: the 256 bytes of internal ram or the lower 256 bytes of external da ta memory. note that the sfrs are not accessible by this method. the upper half of the internal ram can be accessed by indirect addressing only. access to the full 64 kbytes of the active bank of t he external data memory address space is accomplished by us ing the 16-bit data pointer. base register plus index register addressing base register plus index regi ster addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (dptr or pc ) and index register acc. this mode facilitates look-up table accesses. bit addressing direct bit addressing is supp orted for bitaddressable location s: bits of bitaddressable sfrs and the 128 bits in th e bitaddressable area within th e lower internal data ram.
XC800 instruction set user?s manual, v 0.1 4-3 2005-01 4.2 introduction to the instruction set the instruction set is divided in to six basic functional groups: ?arithmetic ?logic ? data transfer ? control transfer (branching) ?boolean ? miscellaneous arithmetic instructions the XC800 microcontrolle rs have four basic math ematical operations. ? addition: add, addc, inc, da ? subtraction: subb, dec ? multiplication: mul ? division: div only 8-bit operations using un signed arithmetic are supported directly. the overflow flag, however, permits the addition and subtractio n operations to handl e both unsigned and signed binary integers . arithmetic can also be perf ormed directly on packed bcd representations. logic instructions the XC800 microcontrollers perform basic logic operations on both bit and byte operands: anl, orl, srl, clr, setb, cpl, rl, rlc, rr, rrc, swap. data transfer instructions data transfer operations are divided into three classes: ? general-purpose ? accumulator-specific ? address-object none of these operations affects the psw flag settings ex cept a pop or mov directly to the psw. control transfer instructions all control transfer operations, some upon a specific conditi on, cause the program execution to continue to a non-sequential location in pr ogram memory. there are three classes of control tr ansfer operations: ? unconditional jumps ? conditional jumps ? subroutine/interrupt calls and returns
XC800 instruction set user?s manual, v 0.1 4-4 2005-01 unconditional jumps transfer co ntrol from the current value of the program counter to the target address. these instructions are: ajmp, ljmp, sjmp and jmp @a + dptr. conditional jumps perform a ju mp contingent upon a specif ic condition. the destination will be within a 256-byte range centered about the starti ng address of the next instruction (? 128 to + 127): jz, jnz, jc, jnc, jb , jnb, jbc, cjne, djnz. there are only 2 types of subroutine call: acal l and lcall. interrupt call is controlled by hardware. return instructions are re t and reti. reti is us ed for return from interrupt, which restores inte rrupt priority to that of the current priority level. boolean instructions the bitaddressable r egisters in both dire ct and sfr space may be manipulated using boolean instructions. the bit ma nipulation instructions allow: ? set bit ?clear bit ? complement bit ? jump if bit is set ? jump if bit is not set ? jump if bit is set and clear bit ? move bit from / to carry addressable bits, or their co mplements, may be logically and-ed or or-ed with the contents of the carry flag. the re sult is stored in the carry bit. miscellaneous instructions these instructions are: ? nop: no operation ? trap: software break command
XC800 instruction set user?s manual, v 0.1 4-5 2005-01 4.3 instructions the XC800 instructions can essentially be condensed to 55 basic operations. these operations are described in deta il in the following sections. 4.3.1 affected flags some instructions affect on e or more of the psw flag s, as generally shown in table 4-2 . in the above table, a ?0? means the flag is always cleare d, a ?1? means the flag is always set and an ?x? means that the state of the fl ag depends on the result of the operation. a blank cell indicates that the flag is unaffected by th e instruction. only the carry, auxiliary carry, and overflow flags are discussed abo ve. the parity bit is always computed from the actual content of t he accumulator. ? cy is set if the operation causes a carry to or a borrow from the resulting high-order bit; otherwise cy is cleared. ? ac is set if the operation resu lts in a carry from the low-order four bits of the result (during addition), or a borrow from the high-o rder bits to the lo w-order bits (during subtraction); otherw ise ac is cleared. ? ov is set if the operation results in a carry to the high-order bit of the result but not a carry from the bit, or vice versa; otherwi se ov is cleared. ov is used in twos complement arithmetic, because it is set wh en the signal result ca nnot be represented in 8 bits. ? p is set if the modu lo-2 sum of the eight bits in th e accumulator is 1 (odd parity); otherwise p is cleared (even pa rity). when a value is wri tten to the psw register, the p bit remains uncha nged, as it always re flects the parity of a. table 4-2 psw flag mo dification (cy,ov,ac) instruction flag instruction flag cy ov ac cy ov ac add x x x setb c 1 addc x x x clr c 0 subb x x x cpl c x mul 0 x anl c,bit x div 0 x anl c,/bit x da x orl c,bit x rrc x orl c,/bit x rlc x mov c,bit x cjne x
XC800 instruction set user?s manual, v 0.1 4-6 2005-01 instructions that directly alter addressed regist ers could affect the othe r status flags if the instruction is applied to the psw. status fl ags can also be modifi ed by bit manipulation. 4.3.2 instruction table table 4-3 lists all the instructions supported by XC800. instruct ions are 1, 2 or 3 bytes long as indicated in the ?bytes? column . each instruction takes 1, 2 or 4 machine cycles to execute (with no wait state). one ma chine cycle comprises 2 cclk clock cycles. table 4-3 instruction table mnemonic description hex code bytes cycles arithmetic add a,rn add register to a 28-2f 1 1 add a,direct add direct byte to a 25 2 1 add a,@ri add indirect memory to a 26-27 1 1 add a,#data add immediate to a 24 2 1 addc a,rn add register to a with carry 38-3f 1 1 addc a,direct add direct byte to a with carry 35 2 1 addc a,@ri add indirect memory to a with carry 36-37 1 1 addc a,#data add immediate to a with carry 34 2 1 subb a,rn subtract register from a with borrow 98-9f 1 1 subb a,direct subtract direct by te from a with borrow 95 2 1 subb a,@ri subtract indirect memory from a with borrow 96-97 1 1 subb a,#data subtract immediate from a with borrow 94 2 1 inc a increment a 04 1 1 inc rn increment register 08-0f 1 1 inc direct increment direct byte 05 2 1 inc @ri increment indirect memory 06-07 1 1 dec a decrement a 14 1 1 dec rn decrement register 18-1f 1 1 dec direct decrement direct byte 15 2 1 dec @ri decrement indirect memory 16-17 1 1
XC800 instruction set user?s manual, v 0.1 4-7 2005-01 inc dptr increment data pointer a3 1 2 mul ab multiply a by b a4 1 4 div ab divide a by b 84 1 4 da a decimal adjust a d4 1 1 logical anl a,rn and register to a 58-5f 1 1 anl a,direct and direct byte to a 55 2 1 anl a,@ri and indirect memory to a 56-57 1 1 anl a,#data and immediate to a 54 2 1 anl direct,a and a to direct byte 52 2 1 anl direct,#data and immediate to direct byte 53 3 2 orl a,rn or register to a 48-4f 1 1 orl a,direct or direct byte to a 45 2 1 orl a,@ri or indirect memory to a 46-47 1 1 orl a,#data or immediate to a 44 2 1 orl direct,a or a to direct byte 42 2 1 orl direct,#data or immediate to direct byte 43 3 2 xrl a,rn exclusive-or register to a 68-6f 1 1 xrl a,direct exclusive-or dire ct byte to a 65 2 1 xrl a,@ri exclusive-or indirect memory to a 66-67 1 1 xrl a,#data exclusive-or immediate to a 64 2 1 xrl direct,a exclusive-or a to direct byte 62 2 1 xrl direct,#data exclusive-or immediate to direct byte 63 3 2 clr a clear a e4 1 1 cpl a complement a f4 1 1 swap a swap nibbles of a c4 1 1 rl a rotate a left 23 1 1 rlc a rotate a left through carry 33 1 1 rr a rotate a right 03 1 1 table 4-3 instruction table (cont?d) mnemonic description hex code bytes cycles
XC800 instruction set user?s manual, v 0.1 4-8 2005-01 rrc a rotate a right through carry 13 1 1 data transfer mov a,rn move register to a e8-ef 1 1 mov a,direct move direct byte to a e5 2 1 mov a,@ri move indirect memory to a e6-e7 1 1 mov a,#data move immediate to a 74 2 1 mov rn,a move a to register f8-ff 1 1 mov rn,direct move direct byte to register a8-af 2 2 mov rn,#data move immediate to register 78-7f 2 1 mov direct,a move a to direct byte f5 2 1 mov direct,rn move register to direct byte 88-8f 2 2 mov direct,direct move direct byte to direct byte 85 3 2 mov direct,@ri move indirect me mory to direct byte 86-87 2 2 mov direct,#data move immediate to direct byte 75 3 2 mov @ri,a move a to indirect memory f6-f7 1 1 mov @ri,direct move direct byte to indirect memory a6-a7 2 2 mov @ri,#data move immediate to indirect memory 76-77 2 1 mov dptr,#data16 move immediate to data pointer 90 3 2 movc a,@a+dptr move code byte relative dptr to a 93 1 2 movc a,@a+pc move code byte re lative pc to a 83 1 2 movx a,@ri move external data (a8) to a e2-e3 1 2 movx a,@dptr move external data (a16) to a e0 1 2 movx @ri,a move a to exte rnal data (a8) f2-f3 1 2 movx @dptr,a move a to exte rnal data (a16) f0 1 2 push direct push direct byte onto stack c0 2 2 pop direct pop direct byte from stack d0 2 2 xch a,rn exchange a and register c8-cf 1 1 table 4-3 instruction table (cont?d) mnemonic description hex code bytes cycles
XC800 instruction set user?s manual, v 0.1 4-9 2005-01 xch a,direct exchange a and direct byte c5 2 1 xch a,@ri exchange a and in direct memory c6-c7 1 1 xchd a,@ri exchange a and i ndirect memory nibble d6-d7 1 1 boolean clr c clear carry c3 1 1 clr bit clear direct bit c2 2 1 setb c set carry d3 1 1 setb bit set direct bit d2 2 1 cpl c complement carry b3 1 1 cpl bit complement direct bit b2 2 1 anl c,bit and direct bit to carry 82 2 2 anl c,/bit and direct bit inverse to carry b0 2 2 orl c,bit or direct bit to carry 72 2 2 orl c,/bit or direct bit inverse to carry a0 2 2 mov c,bit move direct bit to carry a2 2 1 mov bit,c move carry to direct bit 92 2 2 branching acall addr11 absolute call within current 2 k 11->f1 2 2 lcall addr16 long call to addr16 12 3 2 ret return from subroutine 22 1 2 reti return from interrupt routine 32 1 2 ajmp addr11 absolute jump within current 2 k 01->e1 2 2 ljmp addr16 long jump un conditional 02 3 2 sjmp rel short jump to relative address 80 2 2 jc rel jump relative on carry = 1 40 2 2 jnc rel jump relative on carry = 0 50 2 2 jb bit,rel jump relative on direct bit = 1 20 3 2 jnb bit,rel jump relative on direct bit = 0 30 3 2 jbc bit,rel jump relative and clear on direct bit = 1 10 3 2 table 4-3 instruction table (cont?d) mnemonic description hex code bytes cycles
XC800 instruction set user?s manual, v 0.1 4-10 2005-01 jmp @a+dptr jump indirect relative dptr 73 1 2 jz rel jump relative on accumulator = 0 60 2 2 jnz rel jump relative on accumulator = 1 70 2 2 cjne a,direct,rel compare direct memory to accumulator, jump relative if not equal b5 3 2 cjne a,#data,rel compare immediate to accumulator, jump relative if not equal b4 3 2 cjne rn,#data,rel compare immediate to register, jump relative if not equal b8-bf 3 2 cjne @ri,#data,rel compare immediate to indirect memory, jump relative if not equal b6-b7 3 2 djnz rn,rel decrement register and jump relative if not zero d8-df 2 2 djnz direct,rel decrement direct memory and jump relative if not zero d5 3 2 miscellaneous nop no operation 00 1 1 additional instructions ( selected through eo[7:4]) movc @(dptr++),a XC800-specific instruction for software download into program memory: copy from accumulator, then increment dptr a5 1 2 trap XC800-specific software break command a5 1 1 table 4-3 instruction table (cont?d) mnemonic description hex code bytes cycles
XC800 instruction set user?s manual, v 0.1 4-11 2005-01 notes on data addressing modes: rn - working register r0-r7 direct - 128 internal ram locations, special function registers @ri - indirect internal or external ram location addressed by register r0 or r1 #data - 8-bit constant included in instruction #data16 - 16-bit constant included in instruction bit - 128 bit-addressable bits of lower inte rnal data ram, any bit-addressable bits of special function registers a - accumulator notes on program addressing modes: addr16 - destination address for lcall and ljmp may be anywhere within the 64 kbytes of the active bank located in program space. addr11 - destination address for acall and ajmp w ill be within the same 2-kbyte page of program memory as the first byte of the following instruction. rel - sjmp and all conditional jumps incl ude an 8-bit offset byte. range is + 127/? 128 bytes relative to the first byte of the following instruction. all mnemonics copyrighted: intel corporation 1980 4.3.3 instruction definitions the instructions are grouped according to basic operation, and descri bed in alphabetical order according to t he operation mnemonic.
XC800 instruction set user?s manual, v 0.1 4-12 2005-01 acall addr11 function: absolute call description: acall unconditionally calls a subrout ine located at the indicated address. the instruction increments the pc twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice. the destination address is obtained by successively concatenating the five high-or der bits of the incremented pc, opcode bits 7-5, and the second byte of the instruction. the subroutine called must therefore start within the same 2-kbyte bloc k of program memory as the first byte of the instruction following acall. no flags are affected. example: initially sp equals 07 h . the label ?subrtn? is at program memory location 0345 h . after executing the instruction acall subrtn at location 0123 h , sp will contain 09 h , internal ram location 08 h and 09 h will contain 25 h and 01 h , respectively, and the pc will contain 0345 h . operation: acall (pc) (pc) + 2 (sp) (sp) + 1 ((sp)) (pc7-0) (sp) (sp) + 1 ((sp)) (pc15-8) (pc10-0) page address bytes: 2 cycles: 2 encoding: a10 a9 a8 1 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
XC800 instruction set user?s manual, v 0.1 4-13 2005-01 add a, function: add description: add adds the byte vari able indicated to the accumulat or, leaving the result in the accumulator. the carry and auxiliary carry fl ags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleare d otherwise. when adding unsigned integers, the carry flag indicates an overflow occurred. ov is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise ov is cleare d. when adding signed integers, ov indicates a negative number produced as the sum of tw o positive operands, or a positive sum from two negative operands. four source operand addressing modes are allowed: register, direct, register- indirect, or immediate. example: the accumulator holds 0c3 h (11000011 b ) and register 0 holds 0aa h (10101010 b ). the instruction add a,r0 will leave 6d h (01101101 b ) in the accumulator with the ac flag cleared and both the carry flag and ov set to 1. add a,rn operation: add (a) (a) + (rn) bytes: 1 cycles: 1 add a,direct operation: add (a) (a) + (direct) bytes: 2 cycles: 1 encoding: 0 0 1 0 1 r r r encoding: 0 0 1 0 0 1 0 1 direct address
XC800 instruction set user?s manual, v 0.1 4-14 2005-01 add a, @ri operation: add (a) (a) + ((ri)) bytes: 1 cycles: 1 add a, #data operation: add (a) (a) + #data bytes: 2 cycles: 1 encoding: 0 0 1 0 0 1 1 i encoding: 0 0 1 0 0 1 0 0 immediate data
XC800 instruction set user?s manual, v 0.1 4-15 2005-01 addc a, < src-byte> function: add with carry description: addc simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulato r. the carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. when adding unsigned integers, the carry flag indicates an overflow occurred. ov is set if there is a carry out of bit 6 but not out of bit 7, or a carry out of bit 7 but not out of bit 6; otherwise ov is cleare d. when adding signed integers, ov indicates a negative number produced as the sum of two positive operands or a positive sum from two negative operands. four source operand addressing modes are allowed: register, direct, register- indirect, or immediate. example: the accumulator holds 0c3 h (11000011 b ) and register 0 holds 0aa h (10101010 b ) with the carry flag set. the instruction addc a,r0 will leave 6e h (01101110 b ) in the accumulator with ac cleared and both the carry flag and ov set to 1. addc a,rn operation: addc (a) (a) + (c) + (rn) bytes: 1 cycles: 1 addc a,direct operation: addc (a) (a) + (c) + (direct) bytes: 2 cycles: 1 encoding: 0 0 1 1 1 r r r encoding: 0 0 1 1 0 1 0 1 direct address
XC800 instruction set user?s manual, v 0.1 4-16 2005-01 addc a, @ri operation: addc (a) (a) + (c) + ((ri)) bytes: 1 cycles: 1 addc a, #data operation: addc (a) (a) + (c) + #data bytes: 2 cycles: 1 encoding: 0 0 1 1 0 1 1 i encoding: 0 0 1 1 0 1 0 0 immediate data
XC800 instruction set user?s manual, v 0.1 4-17 2005-01 ajmp addr11 function: absolute jump description: ajmp transfers program execution to the indicated address, which is formed at run- time by concatenating the high-or der five bits of the pc ( after incrementing the pc twice), opcode bits 7-5, and the second byte of the instruction. the destination must therefore be within the same 2-kbyte block of program memory as the first byte of the instruction following ajmp. example: the label ?jmpadr? is at program memory location 0123 h . the instruction ajmp jmpadr is at location 0345 h and will load the pc with 0123 h . operation: ajm p (pc) (pc) + 2 (pc10-0) page address bytes: 2 cycles: 2 encoding: a10 a9 a8 0 0 0 0 1 a7 a6 a5 a4 a3 a2 a1 a0
XC800 instruction set user?s manual, v 0.1 4-18 2005-01 anl , function: logical and for byte variables description: anl performs the bitwise logical and operation between the variables indicated and stores the results in the destination vari able. no flags are affected (except p, if = a). the two operands allow six addressing m ode combinations. when the destination is the accumulator, the source can use r egister, direct, regi ster-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: if the accumulator holds 0c3 h (11000011 b ) and register 0 holds 0aa h (10101010 b ) then the instruction anl a,r0 will leave 81 h (10000001 b ) in the accumulator. when the destination is a directly addr essed byte, this instruction will clear combinations of bits in any ram locati on or hardware register. the mask byte determining the pattern of bits to be clea red would either be a constant contained in the instruction or a value comput ed in the accumulator at run-time. the instruction anl p1, #01110011 b will clear bits 7, 3, and 2 of output port 1. anl a,rn operation: anl (a) (a) (rn) bytes: 1 cycles: 1 anl a,direct operation: anl (a) (a) (direct) bytes: 2 cycles: 1 encoding: 0 1 0 1 1 r r r encoding: 0 1 0 1 0 1 0 1 direct address
XC800 instruction set user?s manual, v 0.1 4-19 2005-01 anl a, @ri operation: anl (a) (a) ((ri)) bytes: 1 cycles: 1 anl a, #data operation: anl (a) (a) #data bytes: 2 cycles: 1 anl direct,a operation: anl (direct) (direct) (a) bytes: 2 cycles: 1 encoding: 0 1 0 1 0 1 1 i encoding: 0 1 0 1 0 1 0 0 immediate data encoding: 0 1 0 1 0 0 1 0 direct address
XC800 instruction set user?s manual, v 0.1 4-20 2005-01 anl direct, #data operation: anl (direct) (direct) #data bytes: 3 cycles: 2 encoding: 0 1 0 1 0 0 1 1 direct address immediate data
XC800 instruction set user?s manual, v 0.1 4-21 2005-01 anl c, function: logical and for bit variables description: if the boolean value of the source bit is a logic 0 then clear t he carry flag; otherwise leave the carry flag in its cur rent state. a slash (?/?) preceding the operand in the assembly language indicates that the logica l complement of the addressed bit is used as the source value, but the source bit itself is not affected . no other flags are affected. only direct bit addressing is allowed for the source operand. example: set the carry flag if, and only if, p1.0 = 1, acc.7 = 1, and ov = 0: mov c,p1.0 ; load carry with input pin state anl c,acc.7 ; and carry with accumulator bit 7 anl c,/ov ; and with inverse of overflow flag anl c,bit operation: anl (c) (c) (bit) bytes: 2 cycles: 2 anl c,/bit operation: anl (c) (c) / (bit) bytes: 2 cycles: 2 encoding: 1 0 0 0 0 0 1 0 bit address encoding: 1 0 1 1 0 0 0 0 bit address
XC800 instruction set user?s manual, v 0.1 4-22 2005-01 cjne , < src-byte >, rel function: compare and jump if not equal description: cjne compares the magnitudes of the first two op erands, and branches if their values are not equal. the branch destin ation is computed by adding the signed relative displacement in the last instruct ion byte to the pc, after incrementing the pc to the start of the next instruction. the carry flag is set if the unsigned integer value of is less than the unsigned integer value of ; otherwise, the carry is cleared. neither operand is affected. the first two operands allow four addr essing mode combination s: the accumulator may be compared with any directly addr essed byte or immedi ate data, and any indirect ram location or working regi ster can be compared with an immediate constant. example: the accumulator contains 34 h . register 7 contains 56 h . the first instruction in the sequence cjne r7, # 60h, not_eq ; . . . . . . . . ; r7 = 60 h not_eq jc req_low ; if r7 < 60 h ; . . . . . . . . ; r7 > 60 h sets the carry flag and branches to the inst ruction at label not_eq. by testing the carry flag, this instruction determines whether r7 is greater or less than 60 h . if the data being presented to port 1 is also 34 h , then the instruction wait: cjne a,p1,wait clears the carry flag and continues with t he next instruction in sequence, since the accumulator does equal the data read from p1. (if some other value was input on p1, the program will loop at this point until the p1 data changes to 34 h ).
XC800 instruction set user?s manual, v 0.1 4-23 2005-01 cjne a,direct,rel operation: (pc) (pc) + 3 if (a) < > (direct) then (pc) (pc) + relative offset if (a) < (direct) then (c) 1 else (c) 0 bytes: 3 cycles: 2 cjne a, #data,rel operation: (pc) (pc) + 3 if (a) < > data then (pc) (pc) + relative offset if (a) data then (c) 1 else (c) 0 bytes: 3 cycles: 2 cjne rn, #data, rel operation: (pc) (pc) + 3 if (rn) < > data then (pc) (pc) + relative offset if (rn) < data then (c) 1 else (c) 0 bytes: 3 cycles: 2 encoding: 1 0 1 1 0 1 0 1 direct address rel. address encoding: 1 0 1 1 0 1 0 0 immediate data rel. address encoding: 1 0 1 1 1 r r r immediate data rel. address
XC800 instruction set user?s manual, v 0.1 4-24 2005-01 cjne @ri, #data, rel operation: (pc) (pc) + 3 if ((ri)) < > data then (pc) (pc) + relative offset if ((ri)) < data then (c) 1 else (c) 0 bytes: 3 cycles: 2 encoding: 1 0 1 1 0 1 1 i immediate data rel. address
XC800 instruction set user?s manual, v 0.1 4-25 2005-01 clr a function: clear accumulator description: the accumulator is cleared (all bits set to zer o). no flags are affected. example: the accumulator contains 5c h (01011100 b ). the instruction clr a will leave the accu mulator set to 00 h (00000000 b ). operation: clr (a) 0 bytes: 1 cycles: 1 encoding: 1 1 1 0 0 1 0 0
XC800 instruction set user?s manual, v 0.1 4-26 2005-01 clr bit function: clear bit description: the indicated bit is cleared (reset to zero). no other flags are affected. clr can operate on the carry flag or a ny directly addressable bit. example: port 1 has previously been written with 5d h (01011101 b ). the instruction clr p1.2 will leave the port set to 59 h (01011001 b ). clr c operation: clr (c) 0 bytes: 1 cycles: 1 clr bit operation: clr (bit) 0 bytes: 2 cycles: 1 encoding: 1 1 0 0 0 0 1 1 encoding: 1 1 0 0 0 0 1 0 bit address
XC800 instruction set user?s manual, v 0.1 4-27 2005-01 cpl a function: complement accumulator description: each bit of the accumulator is logica lly complemented (ones complement). bits that previously contained a one are changed to zero and vice versa. no flags are affected. example: the accumulator contains 5c h (01011100 b ). the instruction cpl a will leave the accumu lator set to 0a3 h (10100011 b ). operation: cpl (a) / (a) bytes: 1 cycles: 1 encoding: 1 1 1 1 0 1 0 0
XC800 instruction set user?s manual, v 0.1 4-28 2005-01 cpl bit function: complement bit description: the bit variable specif ied is complemented. a bit that had been a one is changed to zero and vice versa. no other flags are affected. cpl can operate on the carry or any directly addressable bit. note: when this instruction is used to modify an output pin, the value used as the original data will be read from the outp ut data latch, not the input pin. example: port 1 has previously been written with 5d h (01011101 b ). the instruction sequence cpl p1.1 cpl p1.2 will leave the port set to 5b h (01011011 b ). cpl c operation: cpl (bit) / (c) bytes: 1 cycles: 1 cpl bit operation: cpl (c) (bit) bytes: 2 cycles: 1 encoding: 1 0 1 1 0 0 1 1 encoding: 1 0 1 1 0 0 1 0 bit address
XC800 instruction set user?s manual, v 0.1 4-29 2005-01 da a function: decimal adjust accumulator for addition description: da a adjusts the eight-bit value in the ac cumulator resulting from the earlier addition of two variables (each in packed bc d format), producing two four-bit digits. any add or addc instruction may ha ve been used to perf orm the addition. if accumulator bits 3-0 are greater than ni ne (xxxx1010-xxxx1111), or if the ac flag is one, six is added to the accumulator producing the proper bcd digit in the low- order nibble. this internal addition would se t the carry flag if a carry-out of the low- order four-bit field propagated through all hi gh-order bits, but it would not clear the carry flag otherwise. if the carry flag is now set, or if the fo ur high-order bits now exceed nine (1010xxxx- 1111xxxx), these high-order bi ts are incremented by six, producing the proper bcd digit in the high-order nibble. again, this would set the carry flag if there was a carry- out of the high-order bits, but would not clea r the carry. the carry flag thus indicates if the sum of the original two bcd variable s is greater than 100, allowing multiple precision decimal addition. ov is not affected. all of this occurs during the one instruct ion cycle. essentially; this instruction performs the decimal conversion by adding 00 h , 06 h , 60 h , or 66 h to the accumulator, depending on initial accumulator and psw conditions. note: da a cannot simply convert a hexadecimal num ber in the accumulator to bcd notation, nor does da a apply to decimal subtraction. example: the accumulator holds the value 56 h (01010110 b ) representing the packed bcd digits of the decimal number 56. register 3 contains the value 67 h (01100111 b ) representing the packed bcd digits of the dec imal number 67. the carry flag is set. the instruction sequence addc a,r3 da a will first perform a standard twos complement binary additi on, resulting in the value 0be h (10111110 b ) in the accumulator. the carry an d auxiliary carry flags will be cleared. the decimal adjust in struction will then alter the accumulator to the value 24 h (00100100 b ), indicating the packed bcd digits of the decimal number 24, the low- order two digits of the decimal sum of 56, 67, and the carry-in. the carry flag will be set by the decimal adjust instruction, in dicating that a decima l overflow occurred. the true sum 56, 67, and 1 is 124.
XC800 instruction set user?s manual, v 0.1 4-30 2005-01 bcd variables can be incremented or decremented by adding 01 h or 99 h . if the accumulator initially holds 30 h (representing the digits of 30 decimal), then the instruction sequence add a, #99h da a will leave the carry set and 29 h in the accumulator, since 30 + 99 = 129. the low- order byte of the sum can be interpreted to mean 30 ? 1 = 29. operation: da contents of accumulator are bcd if [[(a3-0) > 9] [(ac) = 1]] then (a3-0) (a3-0) + 6 and if [[(a7-4) > 9] [(c) = 1]] then (a7-4) (a7-4) + 6 bytes: 1 cycles: 1 encoding: 1 1 0 1 0 1 0 0
XC800 instruction set user?s manual, v 0.1 4-31 2005-01 dec byte function: decrement description: the variable indicated is d ecremented by 1. an original value of 00 h will underflow to 0ff h . no flags are affected. four operand addressing modes are allowed: accumulator, regi ster, direct, or register-indirect. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: register 0 contains 7f h (01111111 b ). internal ram locations 7e h and 7f h contain 00 h and 40 h , respectively. the instruction sequence dec @r0 dec r0 dec @r0 will leave register 0 set to 7e h and internal ram locations 7e h and 7f h set to 0ff h and 3f h . dec a operation: dec (a) (a) ? 1 bytes: 1 cycles: 1 dec rn operation: dec (rn) (rn) ? 1 bytes: 1 cycles: 1 encoding: 0 0 0 1 0 1 0 0 encoding: 0 0 0 1 1 r r r
XC800 instruction set user?s manual, v 0.1 4-32 2005-01 dec direct operation: dec (direct) (direct) ? 1 bytes: 2 cycles: 1 dec @ri operation: dec ((ri)) ((ri)) ? 1 bytes: 1 cycles: 1 encoding: 0 0 0 1 0 1 0 1 direct address encoding: 0 0 0 1 0 1 1 i
XC800 instruction set user?s manual, v 0.1 4-33 2005-01 div ab function: divide description: div ab divides the unsigned eight-bi t integer in the accumulator by the unsigned eight-bit integer in register b. the accu mulator receives the integer part of the quotient; register b receives the integer remainder. the carry and ov flags will be cleared. exception: if b had originally contained 00 h , the values returned in the accumulator and b register will be undefined and the over flow flag will be set. the carry flag is cleared in any case. example: the accumulator contains 251 (0fb h or 11111011 b ) and b contains 18 (12 h or 00010010 b ). the instruction div ab will leave 13 in th e accumulator (0d h or 00001101 b ) and the value 17 (11 h or 00010001 b ) in b, since 251 = (13x18) + 17. carry and ov will both be cleared. operation: div (a15-8) (b7-0) bytes: 1 cycles: 4 encoding: 1 0 0 0 0 1 0 0 (a) / (b)
XC800 instruction set user?s manual, v 0.1 4-34 2005-01 djnz , function: decrement and jump if not zero description: djnz decrements the location indicated by 1, and branches to the address indicated by the second operand if the result ing value is not zero. an original value of 00 h will underflow to 0ff h . no flags are affected. t he branch destination would be computed by adding the signed relative-dis placement value in the last instruction byte to the pc, after incrementing the pc to the first byte of th e following instruction. the location decremented may be a regist er or directly addressed byte. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: internal ram locations 40 h , 50 h , and 60 h contain the values, 01 h , 70 h , and 15 h , respectively. the instruction sequence djnz 40h,label_1 djnz 50h,label_2 djnz 60h,label_3 will cause a jump to the instruction at label label_2 with the values 00 h , 6f h , and 15 h in the three ram locations. the first jump was not taken because the result was zero. this instruction provides a simple way of executing a program loop a given number of times, or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. the instruction sequence mov r2, #8 toggle: cpl p1.7 djnz r2,toggle will toggle p1.7 eight times, causing four ou tput pulses to appear at bit 7 of output port 1. each pulse will last three machi ne cycles; two for djnz and one to alter the pin.
XC800 instruction set user?s manual, v 0.1 4-35 2005-01 djnz rn,rel operation: djnz (pc) (pc) + 2 (rn) (rn) ? 1 if (rn) > 0 or (rn) < 0 then (pc) (pc) + rel bytes: 2 cycles: 2 djnz direct,rel operation: djnz (pc) (pc) + 2 (direct) (direct) ? 1 if (direct) > 0 or (direct) < 0 then (pc) (pc) + rel bytes: 3 cycles: 2 encoding: 1 1 0 1 1 r r r rel. address encoding: 1 1 0 1 0 1 0 1 direct address rel. address
XC800 instruction set user?s manual, v 0.1 4-36 2005-01 inc function: increment description: inc increments th e indicated variable by 1. an original value of 0ff h will overflow to 00 h . no flags are affected. three addressin g modes are allowed: register, direct, or register-indirect. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: register 0 contains 7e h (01111110 b ). internal ram locations 7e h and 7f h contain 0ff h and 40 h , respectively. the instruction sequence inc @r0 inc r0 inc @r0 will leave register 0 set to 7f h and internal ram locations 7e h and 7f h holding (respectively) 00 h and 41 h . inc a operation: inc (a) (a) + 1 bytes: 1 cycles: 1 inc rn operation: inc (rn) (rn) + 1 bytes: 1 cycles: 1 encoding: 0 0 0 0 0 1 0 0 encoding: 0 0 0 0 1 r r r
XC800 instruction set user?s manual, v 0.1 4-37 2005-01 inc direct operation: inc (direct) (direct) + 1 bytes: 2 cycles: 1 inc @ri operation: inc ((ri)) ((ri)) + 1 bytes: 1 cycles: 1 encoding: 0 0 0 0 0 1 0 1 direct address encoding: 0 0 0 0 0 1 1 i
XC800 instruction set user?s manual, v 0.1 4-38 2005-01 inc dptr function: increment data pointer description: increment the 16- bit data pointer by 1. a 16-bit increment (modulo 2 16 ) is performed; an overflow of the low-order byte of the data pointer (dpl) from 0ff h to 00 h will increment the high-order byte (dph). no flags are affected. this is the only 16-bit regist er which can be incremented. example: registers dph and dpl contain 12 h and 0fe h , respectively. the instruction sequence inc dptr inc dptr inc dptr will change dph and dpl to 13 h and 01 h . operation: inc (dptr) (dptr) + 1 bytes: 1 cycles: 2 encoding: 1 0 1 0 0 0 1 1
XC800 instruction set user?s manual, v 0.1 4-39 2005-01 jb bit,rel function: jump if bit is set description: if the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. the branch destinat ion is computed by adding the signed relative-displacement in the third instructio n byte to the pc, af ter incrementing the pc to the first byte of the next instructio n. the bit tested is not modified. no flags are affected. example: the data present at input port 1 is 11001010 b . the accumulator holds 56 (01010110 b ). the instruction sequence jb p1.2,label1 jb acc.2,label2 will cause program exe cution to branch to the in struction at label label2. operation: jb (pc) (pc) + 3 if (bit) = 1 then (pc) (pc) + rel bytes: 3 cycles: 2 encoding: 0 0 1 0 0 0 0 0 bit address rel. address
XC800 instruction set user?s manual, v 0.1 4-40 2005-01 jbc bit,rel function: jump if bit is set and clear bit description: if the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. in either case, clear the designated bit. the branch destination is computed by adding the signed relative di splacement in the third instruction byte to the pc, after incrementing th e pc to the first byte of t he next instruction. no flags are affected. note: when this instruction is used to test an output pin, the value used as the original data will be read from the outp ut data latch, not the input pin. example: the accumulator holds 56 h (01010110 b ). the instruction sequence jbc acc.3,label1 jbc acc.2,label2 will cause program executio n to continue at th e instruction identi fied by the label label2, with the accumulator modified to 52 h (01010010 b ). operation: jbc (pc) (pc) + 3 if (bit) = 1 then (bit) 0 (pc) (pc) + rel bytes: 3 cycles: 2 encoding: 0 0 0 1 0 0 0 0 bit address rel. address
XC800 instruction set user?s manual, v 0.1 4-41 2005-01 jc rel function: jump if carry is set description: if the carry flag is set, branch to the address indicat ed; otherwise proceed with the next instruction. the branch destination is computed by adding the signed relative- displacement in the second instruction byte to the pc, after incrementing the pc twice. no flags are affected. example: the carry flag is cleared. the instruction sequence jc label1 cpl c jc label2 will set the carry and cause program execution to cont inue at the instruction identified by the label label2. operation: jc (pc) (pc) + 2 if (c) = 1 then (pc) (pc) + rel bytes: 2 cycles: 2 encoding: 0 1 0 0 0 0 0 0 rel. address
XC800 instruction set user?s manual, v 0.1 4-42 2005-01 jmp @a + dptr function: jump indirect description: add the eight-bit unsigned contents of the accumulat or with the sixteen-bit data pointer, and load the resulting sum to the program counter. this will be the address for subsequent instruction fetches. sixt een-bit addition is performed (modulo 2 16 ): a carry-out from the low-order eight bits propagates through the higher-order bits. neither the accumulator nor the data pointer is altered. no flags are affected. example: an even number from 0 to 6 is in the accumulator. the following sequence of instructions will branch to one of four ajmp instructions in a jump table starting at jmp_tbl: mov dptr, #jmp_tbl jmp @a + dptr jmp_tbl: ajmp label0 ajmp label1 ajmp label2 ajmp label3 if the accumulator equals 04 h when starting this sequence, execution will jump to label label2. remember that ajmp is a two-byte instruction, so the jump instructions start at every other address. operation: jmp (pc) (a) + (dptr) bytes: 1 cycles: 2 encoding: 0 1 1 1 0 0 1 1
XC800 instruction set user?s manual, v 0.1 4-43 2005-01 jnb bit,rel function: jump if bit is not set description: if the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. the branch destinat ion is computed by adding the signed relative-displacement in the third instructio n byte to the pc, af ter incrementing the pc to the first byte of the next instruction. the bit tested is not modified. no flags are affected. example: the data present at input port 1 is 11001010 b . the accumulator holds 56 h (01010110 b ). the instruction sequence jnb p1.3,label1 jnb acc.3,label2 will cause program exe cution to cont inue at the instruct ion at label label2. operation: jnb (pc) (pc) + 3 if (bit) = 0 then (pc) (pc) + rel. bytes: 3 cycles: 2 encoding: 0 0 1 1 0 0 0 0 bit address rel. address
XC800 instruction set user?s manual, v 0.1 4-44 2005-01 jnc rel function: jump if carry is not set description: if the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. the branch destinat ion is computed by adding the signed relative-displacement in the second instr uction byte to the pc, after incrementing the pc twice to point to the next instru ction. the carry flag is not modified. example: the carry flag is set. the instruction sequence jnc label1 cpl c jnc label2 will clear the carry and caus e program execution to con tinue at the instruction identified by the label label2. operation: jnc (pc) (pc) + 2 if (c) = 0 then (pc) (pc) + rel bytes: 2 cycles: 2 encoding: 0 1 0 1 0 0 0 0 rel. address
XC800 instruction set user?s manual, v 0.1 4-45 2005-01 jnz rel function: jump if accumulator is not zero description: if any bit of the accumulator is a o ne, branch to the indi cated address; otherwise proceed with the next instruction. the br anch destination is computed by adding the signed relative-displacement in the second instruction byte to the pc, after incrementing the pc twice. the accumulator is not modifi ed. no flags are affected. example: the accumulator originally holds 00 h . the instruction sequence jnz label1 inc a jnz label2 will set the accumulator to 01 h and continue at label label2. operation: jnz (pc) (pc) + 2 if (a) 0 then (pc) (pc) + rel. bytes: 2 cycles: 2 encoding: 0 1 1 1 0 0 0 0 rel. address
XC800 instruction set user?s manual, v 0.1 4-46 2005-01 jz rel function: jump if accumulator is zero description: if all bits of the accumulator are zer o, branch to the address indicated; otherwise proceed with the next instruction. the br anch destination is computed by adding the signed relative-displacement in the second instruction byte to the pc, after incrementing the pc twice. the accumulator is not modifi ed. no flags are affected. example: the accumulator originally contains 01 h . the instruction sequence jz label1 dec a jz label2 will change the ac cumulator to 00 h and cause program execution to continue at the instruction identified by the label label2. operation: jz (pc) (pc) + 2 if (a) = 0 then (pc) (pc) + rel bytes: 2 cycles: 2 encoding: 0 1 1 0 0 0 0 0 rel. address
XC800 instruction set user?s manual, v 0.1 4-47 2005-01 lcall addr16 function: long call description: lcall calls a subroutine located at the indicated address. the instruction adds three to the program counter to generat e the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two. the high-order and low-or der bytes of the pc are then loaded, respectively, with the second and third bytes of the lcal l instruction. program execution continues with the instructi on at this address. the subroutine may therefore begin anywhere in the full 64 -kbyte program memory address space. no flags are affected. example: initially the stack pointer equals 07 h . the label ?subrtn? is assigned to program memory location 1234 h . after executing the instruction lcall subrtn at location 0123 h , the stack pointer will contain 09 h , internal ram locations 08 h and 09 h will contain 26 h and 01 h , and the pc will contain 1234 h . operation: lcall (pc) (pc) + 3 (sp) (sp) + 1 ((sp)) (pc7-0) (sp) (sp) + 1 ((sp)) (pc15-8) (pc) addr15-0 bytes: 3 cycles: 2 encoding: 0 0 0 1 0 0 1 0 addr15 . . addr8 addr7 . . addr0
XC800 instruction set user?s manual, v 0.1 4-48 2005-01 ljmp addr16 function: long jump description: ljmp causes an unconditional branch to the indicated address, by loading the high- order and low-order bytes of the pc (respectively) with the second and third instruction bytes. the desti nation may therefore be anyw here in the full 64-kbyte program memory address space. no flags are affected. example: the label ?jmpadr? is assigned to t he instruction at program memory location 1234 h . the instruction ljmp jmpadr at location 0123 h will load the program counter with 1234 h . operation: ljmp (pc) addr15-0 bytes: 3 cycles: 2 encoding: 0 0 0 0 0 0 1 0 addr15 . . . addr8 addr7 . . . addr0
XC800 instruction set user?s manual, v 0.1 4-49 2005-01 mov , function: move byte variable description: the byte variable i ndicated by the second operand is copied into the location specified by the first operand. the source byte is not affected. no other register or flag is affected. this is by far the most flexible oper ation. fifteen combina tions of source and destination addressing modes are allowed. example: internal ram location 30 h holds 40 h . the value of ram location 40 h is 10 h . the data present at input port 1 is 11001010b (0ca h ). mov r0, #30h ; r0 < = 30h mov a, @r0 ; a < = 40h mov r1,a ; r1 < = 40h mov b, @r1 ; b < = 10 h mov @r1,p1 ; ram (40h) < = 0cah mov p2,p1 ; p2 < = 0cah leaves the value 30 h in register 0, 40 h in both the accumulator and register 1, 10 h in register b, and 0ca h (11001010 b ) both in ram location 40 h and output on port 2. mov a,rn operation: mov (a) (rn) bytes: 1 cycles: 1 mov a,direct *) operation: mov (a) (direct) bytes: 2 cycles: 1 *) mov a,acc is not a valid instruction. the co ntent of the accu mulator after the execution of this instruction is undefined. encoding: 1 1 1 0 1 r r r encoding: 1 1 1 0 0 1 0 1 direct address
XC800 instruction set user?s manual, v 0.1 4-50 2005-01 mov a,@ri operation: mov (a) ((ri)) bytes: 1 cycles: 1 mov a, #data operation: mov (a) #data bytes: 2 cycles: 1 mov rn,a operation: mov (rn) (a) bytes: 1 cycles: 1 mov rn,direct operation: mov (rn) (direct) bytes: 2 cycles: 2 encoding: 1 1 1 0 0 1 1 i encoding: 0 1 1 1 0 1 0 0 immediate data encoding: 1 1 1 1 1 r r r encoding: 1 0 1 0 1 r r r direct address
XC800 instruction set user?s manual, v 0.1 4-51 2005-01 mov rn, #data operation: mov (rn) #data bytes: 2 cycles: 1 mov direct,a operation: mov (direct) (a) bytes: 2 cycles: 1 mov direct,rn operation: mov (direct) (rn) bytes: 2 cycles: 2 mov direct,direct operation: mov (direct) (direct) bytes: 3 cycles: 2 encoding: 0 1 1 1 1 r r r immediate data encoding: 1 1 1 1 0 1 0 1 direct address encoding: 1 0 0 0 1 r r r direct address encoding: 1 0 0 0 0 1 0 1 dir.addr. (src) dir.addr. (dest)
XC800 instruction set user?s manual, v 0.1 4-52 2005-01 mov direct, @ ri operation: mov (direct) ((ri)) bytes: 2 cycles: 2 mov direct, #data operation: mov (direct) #data bytes: 3 cycles: 2 mov @ ri,a operation: mov ((ri)) (a) bytes: 1 cycles: 1 mov @ ri,direct operation: mov ((ri)) (direct) bytes: 2 cycles: 2 encoding: 1 0 0 0 0 1 1 i direct address encoding: 0 1 1 1 0 1 0 1 direct address immediate data encoding: 1 1 1 1 0 1 1 i encoding: 1 0 1 0 0 1 1 i direct address
XC800 instruction set user?s manual, v 0.1 4-53 2005-01 mov @ ri,#data operation: mov ((ri)) #data bytes: 2 cycles: 1 encoding: 0 1 1 1 0 1 1 i immediate data
XC800 instruction set user?s manual, v 0.1 4-54 2005-01 mov , function: move bit data description: the boolean variable indicated by the second operand is copied into the location specified by the first operand. one of th e operands must be the carry flag; the other may be any directly addressable bit. no other register or flag is affected. example: the carry flag is originally set. th e data present at input port 3 is 11000101 b . the data previously written to output port 1 is 35 h (00110101 b ). mov p1.3,c mov c,p3.3 mov p1.2,c will leave the carry clear ed and change port 1 to 39 h (00111001 b ). mov c,bit operation: mov (c) (bit) bytes: 2 cycles: 1 mov bit,c operation: mov (bit) (c) bytes: 2 cycles: 2 encoding: 1 0 1 0 0 0 1 0 bit address encoding: 1 0 0 1 0 0 1 0 bit address
XC800 instruction set user?s manual, v 0.1 4-55 2005-01 mov dptr, #data16 function: load data pointer with a 16-bit constant description: the data pointer is loaded with the 16 -bit constant indicated. the 16-bit constant is loaded into the second and third bytes of th e instruction. the second byte (dph) is the high-order byte, while the third byte (d pl) holds the low-order byte. no flags are affected. this is the only instruction that moves 16 bits of data at once. example: the instruction mov dptr, #1234h will load the value 1234 h into the data pointer: dph will hold 12 h and dpl will hold 34 h . operation: mov (dptr) #data15-0 dph dpl #data15-8 #data7-0 bytes: 3 cycles: 2 encoding: 1 0 0 1 0 0 0 0 immed. data 15 . . . 8 immed. data 7 . . . 0
XC800 instruction set user?s manual, v 0.1 4-56 2005-01 movc a, @a + function: read code byte description: load the accumulat or with a code byte, or constant from program memory. the address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents and the contents of a sixteen-bit base register, which may be either the data pointer or the pc. in the latter case, the pc is incremented to the address of the following instruction before being adde d to the accumulator; otherwise the base register is not altered. sixteen-bit addition is performed so a carry-out from the low- order eight bits may propagate through hi gher-order bits. no flags are affected. example: a value between 0 and 3 is in the ac cumulator. the followin g instructions will translate the value in the accumulator to one of four values defined by the db (define byte) directive. rel_pc: inc a movc a, @a + pc ret db 66h db 77h db 88h db 99h if the subroutine is called with the accumulator equal to 01 h , it will return with 77 h in the accumulator. the inc a before t he movc instruction is needed to ?get around? the ret instruction above the tabl e. if several bytes of code separated the movc from the table, the correspondi ng number would be added to the accumulator instead. movc a, @a + dptr operation: movc (a) ((a) + (dptr)) bytes: 1 cycles: 2 encoding: 1 0 0 1 0 0 1 1
XC800 instruction set user?s manual, v 0.1 4-57 2005-01 movc a, @a + pc operation: movc (pc) (pc) + 1 (a) ((a) + (pc)) bytes: 1 cycles: 2 encoding: 1 0 0 0 0 0 1 1
XC800 instruction set user?s manual, v 0.1 4-58 2005-01 movc @(dptr++), a function: write code byte description: store the byte content of accumulator to program memory. the address in program memory is pointed to by the data pointer. the data pointer is incremented by hardware, after the write. no flags are affected. example: store value e4 h to program memory at 1000 h . opcode e4 h is the clr a instruction. mov a, #e4h mov dptr,#1000h movc @(dptr++), a ; write clr a to program memory at 1000 h operation: movc ((dptr)) (a) (dptr) = (dptr) + 1 bytes: 1 cycles: 2 note: this instruction is XC800-specific, th erefore may not be supported by standard 8051 assembler. in such cases, this can be workaround by direct byte declaration and definition e.g. ?.byte #a5 h ? (syntax is assembler dependent). note: this instruction shares the same opcode with another XC800-specific instruction trap. movc is selected only if eo.trap_en = 0. encoding: 1 0 1 0 0 1 0 1
XC800 instruction set user?s manual, v 0.1 4-59 2005-01 movx , function: move external description: the movx instruct ions transfer data between the accumulator and a byte of external data memory, hence the ?x? appended to mov. there are two types of instructions, differing in whet her they provide an 8-bit or 16-bit indirect address to the external data ram. in the first type, the contents of r0 or r1 in the current register bank provide an 8-bit address on the low-byte address port . eight bits are sufficient for external l/o expansion decoding or a relatively small ram array. for somewhat larger arrays, any output port pins can be used to output higher-order address bits. these pins would be controlled by an out put instruction preceding the movx. in the second type of movx instructio ns, the data pointer generates a 16-bit address. the high-byte address port outputs the high-order eight address bits (the contents of dph) while the low-byte add ress port outputs the low-order eight address bits (dpl). the special functi on registers of th e address ports are unaffected and retain the previous contents. this form of access is faster and more efficient when accessing very large data arrays (up to 64 kbytes), since no additional instructions are ne eded to set up the output ports. it is possible in some situations to mix the two movx types. a large ram array with its high-order address lines driven on the address port can be addressed via the data pointer, or with code to output high -order address bits to the high-byte port followed by a movx instruction using r0 or r1. example: an external 256-byte ram using multiplexed address/data lines is connected to the low-byte address port. port 3 provides cont rol lines for the external ram. other ports (such as the high-byte address port) are used for normal l/o. registers 0 and 1 contain 12 h and 34 h . location 34 h of the external ram holds the value 56 h . the instruction sequence movx a, @r1 movx @r0,a copies the value 56 h into both the accumulator and external ram location 12 h .
XC800 instruction set user?s manual, v 0.1 4-60 2005-01 movx a,@ri operation: movx (a) ((ri)) bytes: 1 cycles: 2 movx a,@dptr operation: movx (a) ((dptr)) bytes: 1 cycles: 2 movx @ri,a operation: movx ((ri)) (a) bytes: 1 cycles: 2 movx @dptr,a operation: movx ((dptr)) (a) bytes: 1 cycles: 2 encoding: 1 1 1 0 0 0 1 i encoding: 1 1 1 0 0 0 0 0 encoding: 1 1 1 1 0 0 1 i encoding: 1 1 1 1 0 0 0 0
XC800 instruction set user?s manual, v 0.1 4-61 2005-01 mul ab function: multiply description: mul ab multiplies the unsigned eight-bi t integers in the accumulator and register b. the low-order byte of the sixteen-bit pr oduct is left in the accumulator, and the high-order byte in b. if the product is greater than 255 (0ff h ) the overflow flag is set; otherwise it is cleared. th e carry flag is always cleared. example: originally the accumulator holds the value 80 (50 h ). register b holds the value 160 (0a0 h ). the instruction mul ab will give the product 12,800 (3200 h ), so b is changed to 32 h (00110010 b ) and the accumulator is cleared. the overflow flag is set, carry is cleared. operation: mul (a7-0) (b15-8) bytes: 1 cycles: 4 encoding: 1 0 1 0 0 1 0 0 (a) x (b)
XC800 instruction set user?s manual, v 0.1 4-62 2005-01 nop function: no operation description: execution continues at the following instruction. othe r than the pc, no registers or flags are affected. example: it is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles. a simple setb/clr sequence would generate a one-cycle pulse, so four additional cycles must be inserted. this may be done (assuming no interrupts are enabled) with the instruction sequence clr p2.7 nop nop nop nop setb p2.7 operation: nop bytes: 1 cycles: 1 encoding: 0 0 0 0 0 0 0 0
XC800 instruction set user?s manual, v 0.1 4-63 2005-01 orl , function: logical or for byte variables description: orl performs the bi twise logical or operation be tween the indicated variables, storing the results in the destination by te. no flags are affected (except p, if = a). the two operands allow six addressing m ode combinations. when the destination is the accumulator, the source can use r egister, direct, regi ster-indirect, or immediate addressing; when the destination is a direct address, the source can be the accumulator or immediate data. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: if the accumulator holds 0c3 h (11000011 b ) and r0 holds 55 h (01010101 b ) then the instruction orl a,r0 will leave the a ccumulator holding the value 0d7 h (11010111 b ). when the destination is a directly addressed byte, the instruction can set combinations of bits in any ram location or hardware register. the pattern of bits to be set is determined by a mask byte, which may be either a constant data value in the instruction or a variable compute d in the accumulator at run-time. the instruction orl p1,#00110010 b will set bits 5, 4, and 1 of output port 1. orl a,rn operation: orl (a) (a) (rn) bytes: 1 cycles: 1 encoding: 0 1 0 0 1 r r r
XC800 instruction set user?s manual, v 0.1 4-64 2005-01 orl a,direct operation: orl (a) (a) (direct) bytes: 2 cycles: 1 orl a,@ri operation: orl (a) (a) ((ri)) bytes: 1 cycles: 1 orl a,#data operation: orl (a) (a) #data bytes: 2 cycles: 1 orl direct,a operation: orl (direct) (direct) (a) bytes: 2 cycles: 1 encoding: 0 1 0 0 0 1 0 1 direct address encoding: 0 1 0 0 0 1 1 i encoding: 0 1 0 0 0 1 0 0 immediate data encoding: 0 1 0 0 0 0 1 0 direct address
XC800 instruction set user?s manual, v 0.1 4-65 2005-01 orl direct, #data operation: orl (direct) (direct) #data bytes: 3 cycles: 2 encoding: 0 1 0 0 0 0 1 1 direct address immediate data
XC800 instruction set user?s manual, v 0.1 4-66 2005-01 orl c, function: logical or for bit variables description: set the carry flag if the boolean value is a logic 1; leave the carry in its current state otherwise. a slash (?/?) preceding the operand in the assembly language indicates that the logical complement of the addr essed bit is used as the source value, but the source bit itself is not affected. no other flags are affected. example: set the carry flag if, and only if, p1.0 = 1, acc.7 = 1, or ov = 0: mov c,p1.0 ; load carry with input pin p1.0 orl c,acc.7 ; or carry with the accumulator bit 7 orl c,/ov ; or carry with the inverse of ov orl c,bit operation: orl (c) (c) (bit) bytes: 2 cycles: 2 orl c,/bit operation: orl (c) (c) / (bit) bytes: 2 cycles: 2 encoding: 0 1 1 1 0 0 1 0 bit address encoding: 1 0 1 0 0 0 0 0 bit address
XC800 instruction set user?s manual, v 0.1 4-67 2005-01 pop direct function: pop from stack description: the contents of the internal ram lo cation addressed by the stack pointer is read, and the stack pointer is decremented by one . the value read is the transfer to the directly addressed byte indi cated. no flags are affected. example: the stack pointer originally contains the value 32 h , and internal ram locations 30 h through 32 h contain the values 20 h , 23 h , and 01 h , respectively. the instruction sequence pop dph pop dpl will leave the stack pointe r equal to the value 30 h and the data pointer set to 0123 h . at this point the instruction pop sp will leave the stack pointer set to 20 h . note that in this special case the stack pointer was decremented to 2f h before being loaded with the value popped (20 h ). operation: pop (direct) ((sp)) (sp) (sp) ? 1 bytes: 2 cycles: 2 encoding: 1 1 0 1 0 0 0 0 direct address
XC800 instruction set user?s manual, v 0.1 4-68 2005-01 push direct function: push onto stack description: the stack pointer is incremented by one. the content of the indicated variable is then copied into the internal ram location addressed by the stack pointer. otherwise no flags are affected. example: on entering an interrupt routine the stack pointer contains 09 h . the data pointer holds the value 0123 h . the instruction sequence push dpl push dph will leave the stack pointer set to 0b h and store 23 h and 01 h in internal ram locations 0a h and 0b h , respectively. operation: push (sp) (sp) + 1 ((sp)) (direct) bytes: 2 cycles: 2 encoding: 1 1 0 0 0 0 0 0 direct address
XC800 instruction set user?s manual, v 0.1 4-69 2005-01 ret function: return from subroutine description: ret pops the high and low-order bytes of the pc successively from the stack, decrementing the stack pointer by tw o. program execution continues at the resulting address, generally the instruct ion immediately following an acall or lcall. no flags are affected. example: the stack pointer originally contains the value 0b h . internal ram locations 0a h and 0b h contain the values 23 h and 01 h , respectively. the instruction ret will leave the stack point er equal to the value 09 h . program execution will continue at location 0123 h . operation: ret (pc15-8) ((sp)) (sp) (sp) ? 1 (pc7-0) ((sp)) (sp) (sp) ? 1 bytes: 1 cycles: 2 encoding: 0 0 1 0 0 0 1 0
XC800 instruction set user?s manual, v 0.1 4-70 2005-01 reti function: return from interrupt description: reti pops the high and low-order byt es of the pc successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. the stack pointer is left decremented by two. no other registers are affected; the psw is not automatically restored to its pre-interrupt status. program execution continues at the resulting address, which is generally the instruction immediately after the point at which the interrupt request was detected. if a lower or same-level interrupt is pendi ng when the reti instruction is executed, that one instruction will be executed before the pending interrupt is processed. example: the stack pointer originally contains the value 0b h . an interrupt was detected during the instruction ending at location 0122 h . internal ram locations 0a h and 0b h contain the values 23 h and 01 h , respectively. the instruction reti will leave the stack pointer equal to 09 h and return program execution to location 0123 h . operation: reti (pc15-8) ((sp)) (sp) (sp) ? 1 (pc7-0) ((sp)) (sp) (sp) ? 1 bytes: 1 cycles: 2 encoding: 0 0 1 1 0 0 1 0
XC800 instruction set user?s manual, v 0.1 4-71 2005-01 rl a function: rotate accumulator left description: the eight bits in the accumulator are rotated one bit to the left. bit 7 is rotated into the bit 0 position. no flags are affected. example: the accumulator holds the value 0c5 h (11000101 b ). the instruction rl a leaves the accumulator holding the value 8b h (10001011 b ) with the carry unaffected. operation: rl (an + 1) (an) n = 0-6 (a0) (a7) bytes: 1 cycles: 1 encoding: 0 0 1 0 0 0 1 1
XC800 instruction set user?s manual, v 0.1 4-72 2005-01 rlc a function: rotate accumulator left through carry flag description: the eight bits in th e accumulator and the carry flag are together rotated one bit to the left. bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position. no other flags are affected. example: the accumulator holds the value 0c5 h (11000101 b ), and the carry is zero. the instruction rlc a leaves the accumulator holding the value 8a h (10001010b) with the carry set. operation: rlc (an + 1) (an) n = 0-6 (a0) (c) (c) (a7) bytes: 1 cycles: 1 encoding: 0 0 1 1 0 0 1 1
XC800 instruction set user?s manual, v 0.1 4-73 2005-01 rr a function: rotate accumulator right description: the eight bits in the accumulator are rotated one bit to the right. bit 0 is rotated into the bit 7 position. no flags are affected. example: the accumulator holds the value 0c5 h (11000101 b ). the instruction rr a leaves the accumulator holding the value 0e2 h (11100010 b ) with the carry unaffected. operation: rr (an) (an + 1) n = 0-6 (a7) (a0) bytes: 1 cycles: 1 encoding: 0 0 0 0 0 0 1 1
XC800 instruction set user?s manual, v 0.1 4-74 2005-01 rrc a function: rotate accumulator right through carry flag description: the eight bits in th e accumulator and the carry flag are together rotated one bit to the right. bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position. no other flags are affected. example: the accumulator holds the value 0c5 h (11000101 b ), the carry is zero. the instruction rrc a leaves the accumulator holding the value 62 h (01100010 b ) with the carry set. operation: rrc (an) (an + 1) n=0-6 (a7) (c) (c) (a0) bytes: 1 cycles: 1 encoding: 0 0 0 1 0 0 1 1
XC800 instruction set user?s manual, v 0.1 4-75 2005-01 setb function: set bit description: setb sets th e indicated bit to one. setb can operate on th e carry flag or any directiy addressable bit. no other flags are affected. example: the carry flag is cleared. output port 1 has been written with the value 34 h (00110100 b ). the instructions setb c setb p1.0 will leave the carry flag set to 1 and change the data output on port 1 to 35 h (00110101 b ). setb c operation: setb (c) 1 bytes: 1 cycles: 1 setb bit operation: setb (bit) 1 bytes: 2 cycles: 1 encoding: 1 1 0 1 0 0 1 1 encoding: 1 1 0 1 0 0 1 0 bit address
XC800 instruction set user?s manual, v 0.1 4-76 2005-01 sjmp rel function: short jump description: program control branches unconditio nally to the address indicated. the branch destination is computed by adding the signed displacement in the second instruction byte to the pc, after incrementi ng the pc twice. therefore, the range of destinations allowed is from 128 bytes pr eceding this instruction to 127 bytes following it. example: the label ?reladr? is assigned to an instruction at program memory location 0123 h . the instruction sjmp reladr will assemble into location 0100 h . after the instruction is executed, the pc will contain the value 0123 h . note: under the above conditions the instru ction following sjmp will be at 102 h . therefore, the displacement byte of the i nstruction will be the relative offset (0123 h - 0102 h ) = 21 h . in other words, an sjmp with a displacement of 0fe h would be a one-instruction infinite loop. operation: sjmp (pc) (pc) + 2 (pc) (pc) + rel bytes: 2 cycles: 2 encoding: 1 0 0 0 0 0 0 0 rel. address
XC800 instruction set user?s manual, v 0.1 4-77 2005-01 subb a, function: subtract with borrow description: subb subtracts th e indicated variable and the ca rry flag together from the accumulator, leaving the result in the accumulator. subb sets the carry (borrow) flag if a borrow is needed for bit 7, and clears c otherwise. (if c was set before executing a subb instruction, this i ndicates that a borrow was needed for the previous step in a multiple precision subtra ction, so the carry is subtracted from the accumulator along with the source operand). ac is set if a borrow is needed for bit 3, and cleared otherwise. ov is set if a borrow is needed into bit 6 but not into bit 7, or into bit 7 but not bit 6. when subtracting signed integers ov indi cates a negative number produced when a negative value is subtracted from a posi tive value, or a positive result when a positive number is subtract ed from a negative number. the source operand allows four address ing modes: register, direct, register- indirect, or immediate. example: the accumulator holds 0c9 h (11001001 b ), register 2 holds 54 h (01010100 b ), and the carry flag is set. the instruction subb a,r2 will leave the value 74 h (01110100 b ) in the accumulator, with the carry flag and ac cleared but ov set. notice that 0c9 h minus 54 h is 75 h . the difference between this and the above result is due to the (borrow) flag being set before the operation. if the state of the carry is not known before starting a single or multiple-precision subtraction, it should be explicitly cleared by a clr c instruction. subb a,rn operation: subb (a) (a) ? (c) ? (rn) bytes: 1 cycles: 1 encoding: 1 0 0 1 1 r r r
XC800 instruction set user?s manual, v 0.1 4-78 2005-01 subb a,direct operation: subb (a) (a) ? (c) ? (direct) bytes: 2 cycles: 1 subb a, @ ri operation: subb (a) (a) ? (c) ? ((ri)) bytes: 1 cycles: 1 subb a, #data operation: subb (a) (a) ? (c) ? #data bytes: 2 cycles: 1 encoding: 1 0 0 1 0 1 0 1 direct address encoding: 1 0 0 1 0 1 1 i encoding: 1 0 0 1 0 1 0 0 immediate data
XC800 instruction set user?s manual, v 0.1 4-79 2005-01 swap a function: swap nibbles within the accumulator description: swap a interchanges the low and hi gh-order nibbles (four- bit fields) of the accumulator (bits 3-0 and bits 7-4). the ope ration can also be thought of as a four- bit rotate instruction. no flags are affected. example: the accumulator holds the value 0c5 h (11000101 b ). the instruction swap a leaves the accumulator holding the value 5c h (01011100 b ). operation: swap (a3-0) (a7-4), (a7-4) (a3-0) bytes: 1 cycles: 1 encoding: 1 1 0 0 0 1 0 0
XC800 instruction set user?s manual, v 0.1 4-80 2005-01 trap function: software break description: assert a software break . enters debug mode at the end of phase 1 of the machine cycle. no flags are affected. example: if eo.trap_en = 1, opcode a5 h is a trap instruction. mov a, #55h trap ; break inc a operation: trap bytes: 1 cycles: 1 note: this instruction is XC800-specific, th erefore may not be supported by standard 8051 assembler. in such cases, this can be workaround by direct byte declaration and definition e.g. ?.byte #a5 h ? (syntax is assembler dependent). note: this instruction shares the same opcode with another XC800-specific instruction movc @(dptr++),a. trap is selected only if eo.trap_en = 1. encoding: 1 0 1 0 0 1 0 1
XC800 instruction set user?s manual, v 0.1 4-81 2005-01 xch a, function: exchange accumulator with byte variable description: xch loads the accumulator with the c ontents of the indicated variable, at the same time writing the original ac cumulator contents to the in dicated variable. the source/ destination operand can use register, direct, or register-indirect addressing. example: r0 contains the address 20 h . the accumulator holds the value 3f h (00111111 b ). internal ram location 20 h holds the value 75 h (01110101 b ). the instruction xch a, @r0 will leave ram location 20 h holding the value 3f h (00111111 b ) and 75 h (01110101 b ) in the accumulator. xch a,rn operation: xch (a) (rn) bytes: 1 cycles: 1 xch a,direct operation: xch (a) (direct) bytes: 2 cycles: 1 encoding: 1 1 0 0 1 r r r encoding: 1 1 0 0 0 1 0 1 direct address
XC800 instruction set user?s manual, v 0.1 4-82 2005-01 xch a, @ ri operation: xch (a) ((ri)) bytes: 1 cycles: 1 encoding: 1 1 0 0 0 1 1 i
XC800 instruction set user?s manual, v 0.1 4-83 2005-01 xchd a,@ri function: exchange digit description: xchd exchanges the low-order nibble of the accumulator (bits 3-0, generally representing a hexadecimal or bcd digit), with that of the internal ram location indirectly addressed by the specified regist er. the high-order nibbles (bits 7-4) of each register are not affect ed. no flags are affected. example: r0 contains the address 20 h . the accumulator holds the value 36 h (00110110 b ). internal ram location 20 h holds the value 75 h (01110101 b ). the instruction xchd a, @ r0 will leave ram location 20 h holding the value 76 h (01110110 b ) and 35 h (00110101 b ) in the accumulator. operation: xchd (a3-0) ((ri)3-0) bytes: 1 cycles: 1 encoding: 1 1 0 1 0 1 1 i
XC800 instruction set user?s manual, v 0.1 4-84 2005-01 xrl , function: logical exclusive or for byte variables description: xrl performs the bitwise logical exclusive or operation between the indicated variables, storing the results in the destination. no flags are affected (except p, if = a). the two operands allow six addressing m ode combinations. when the destination is the accumulator, the source can use r egister, direct, regi ster-indirect, or immediate addressing; when the destination is a direct address, the source can be accumulator or immediate data. note: when this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins. example: if the accumulator holds 0c3 h (11000011 b ) and register 0 holds 0aa h (10101010b) then the instruction xrl a,r0 will leave the accumula tor holding the value 69 h (01101001 b ). when the destination is a directly addre ssed byte, this instruction can complement combinations of bits in any ram location or hardware register. the pattern of bits to be complemented is then determined by a mask byte, either a constant contained in the instruction or a variable compute d in the accumulator at run-time. the instruction xrl p1,#00110001b will complement bits 5, 4, and 0 of output port 1. xrl a,rn operation: xrl2 (a) (a) (rn) bytes: 1 cycles: 1 encoding: 0 1 1 0 1 r r r v
XC800 instruction set user?s manual, v 0.1 4-85 2005-01 xrl a,direct operation: xrl (a) (a) (direct) bytes: 2 cycles: 1 xrl a, @ ri operation: xrl (a) (a) ((ri)) bytes: 1 cycles: 1 xrl a, #data operation: xrl (a) (a) #data bytes: 2 cycles: 1 xrl direct,a operation: xrl (direct) (direct) (a) bytes: 2 cycles: 1 encoding: 0 1 1 0 0 1 0 1 direct address encoding: 0 1 1 0 0 1 1 i encoding: 0 1 1 0 0 1 0 0 immediate data encoding: 0 1 1 0 0 0 1 0 direct address v v v v
XC800 instruction set user?s manual, v 0.1 4-86 2005-01 xrl direct, #data operation: xrl (direct) (direct) #data bytes: 3 cycles: 2 encoding: 0 1 1 0 0 0 1 1 direct address immediate data v
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